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updates the release notes
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distribution/ReleaseNotes.txt

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Release Notes
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HEAD, planned as v0.26
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v0.26, released on 25. Jan. 2021
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- Performance improvement of the simulation start.
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- Improved the gui to modify the k-map layout.
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- Improved the layout of fsm transitions in the fsm editor.
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- Generic circuits are easier to debug: It is possible now to create
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a specific, concrete circuit from a generic one.
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- In generic circuits it is now possible to add components and
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wires to the circuit.
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wires to the circuit programmatically.
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- It is now possible to use a probe as output in a test case.
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- Adds undo to text fields
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- Fixed a bug in the Demuxer Verilog template that causes problems

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