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2 | 2 |
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3 | 3 | ## Initialization sequence
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4 | 4 |
|
5 |
| -* display_set_reset(); |
6 |
| -* sleep(10); |
7 |
| -* display_clear_reset(); |
8 |
| -* sleep(20); |
9 |
| -* display_set_reset(); |
10 |
| -* sleep(20); |
| 5 | + display_set_reset(); |
| 6 | + sleep(10); |
| 7 | + display_clear_reset(); |
| 8 | + sleep(20); |
| 9 | + display_set_reset(); |
| 10 | + sleep(20); |
11 | 11 |
|
12 |
| -* display_send_command(0x11); // SLPOUT: Sleep out |
13 |
| -* sleep(120) |
14 |
| -* display_send_command(0x36); // MADCTL: Memory access control |
15 |
| -* display_send_data(0x0); |
16 |
| -* display_send_command(0x3a); // COLMOD: Interface pixel format |
17 |
| -* display_send_data(0x5); // Set: 0x5 (16 bit/pixel) (should be 0x55) |
18 |
| -* display_send_command(0xb2); // PORCTRL: Porch setting |
19 |
| -* display_send_data(0xc); // Default value |
20 |
| -* display_send_data(0xc); |
21 |
| -* display_send_data(0x0); |
22 |
| -* display_send_data(0x33); |
23 |
| -* display_send_data(0x33); |
24 |
| -* display_send_command(0xb7); // GCTRL: Gate control |
25 |
| -* display_send_data(0x35); // Default value |
26 |
| -* display_send_command(0xbb); // VCOMS: VCOMS setting |
27 |
| -* display_send_data(0x28); // Set: 1.1 V (default 0.9 V) |
28 |
| -* display_send_command(0xc0); // LCMCTRL: LCM control |
29 |
| -* display_send_data(0x2c); // Default value |
30 |
| -* display_send_command(0xc2); // VDVVRHEN: VDV and VRH command enable |
31 |
| -* display_send_data(0x1); // Default value |
32 |
| -* display_send_command(0xc3); // VRHS: VRH set |
33 |
| -* display_send_data(0xb); // Default value |
34 |
| -* display_send_command(0xc4); // VDVS: VDV set |
35 |
| -* display_send_data(0x20); // Default value |
36 |
| -* display_send_command(0xc6); // FRCTRL2: Frame rate control in normal mode |
37 |
| -* display_send_data(0xf); // Default value |
38 |
| -* display_send_command(0xd0); // PWCTRL1: Power control 1 |
39 |
| -* display_send_data(0xa4); // Set: AVDD 6.8 V, AVCL -4.8 V, VDDS 2.3 V |
40 |
| -* display_send_data(0xa1); |
41 |
| -* display_send_command(0xe0); // PVGAMCTRL: Positive voltage gamma control |
42 |
| -* display_send_data(0xd0); // Set |
43 |
| -* display_send_data(0x1); |
44 |
| -* display_send_data(0x8); |
45 |
| -* display_send_data(0xf); |
46 |
| -* display_send_data(0x11); |
47 |
| -* display_send_data(0x2a); |
48 |
| -* display_send_data(0x36); |
49 |
| -* display_send_data(0x55); |
50 |
| -* display_send_data(0x44); |
51 |
| -* display_send_data(0x3a); |
52 |
| -* display_send_data(0xb); |
53 |
| -* display_send_data(0x6); |
54 |
| -* display_send_data(0x11); |
55 |
| -* display_send_data(0x20); |
56 |
| -* display_send_command(0xe1); // NVGAMCTRL: Negative voltage gamma control |
57 |
| -* display_send_data(0xd0); // Set |
58 |
| -* display_send_data(0x2); |
59 |
| -* display_send_data(0x7); |
60 |
| -* display_send_data(0xa); |
61 |
| -* display_send_data(0xb); |
62 |
| -* display_send_data(0x18); |
63 |
| -* display_send_data(0x34); |
64 |
| -* display_send_data(0x43); |
65 |
| -* display_send_data(0x4a); |
66 |
| -* display_send_data(0x2b); |
67 |
| -* display_send_data(0x1b); |
68 |
| -* display_send_data(0x1c); |
69 |
| -* display_send_data(0x22); |
70 |
| -* display_send_data(0x1f); |
71 |
| -* display_send_command(0x29); // DISPON: Display on |
72 |
| -* display_send_command(0x2c); // RAMWR: Memory write |
| 12 | + display_send_command(0x11); // SLPOUT: Sleep out |
| 13 | + sleep(120) |
| 14 | + display_send_command(0x36); // MADCTL: Memory access control |
| 15 | + display_send_data(0x0); |
| 16 | + display_send_command(0x3a); // COLMOD: Interface pixel format |
| 17 | + display_send_data(0x5); // Set: 0x5 (16 bit/pixel) (should be 0x55) |
| 18 | + display_send_command(0xb2); // PORCTRL: Porch setting |
| 19 | + display_send_data(0xc); // Default value |
| 20 | + display_send_data(0xc); |
| 21 | + display_send_data(0x0); |
| 22 | + display_send_data(0x33); |
| 23 | + display_send_data(0x33); |
| 24 | + display_send_command(0xb7); // GCTRL: Gate control |
| 25 | + display_send_data(0x35); // Default value |
| 26 | + display_send_command(0xbb); // VCOMS: VCOMS setting |
| 27 | + display_send_data(0x28); // Set: 1.1 V (default 0.9 V) |
| 28 | + display_send_command(0xc0); // LCMCTRL: LCM control |
| 29 | + display_send_data(0x2c); // Default value |
| 30 | + display_send_command(0xc2); // VDVVRHEN: VDV and VRH command enable |
| 31 | + display_send_data(0x1); // Default value |
| 32 | + display_send_command(0xc3); // VRHS: VRH set |
| 33 | + display_send_data(0xb); // Default value |
| 34 | + display_send_command(0xc4); // VDVS: VDV set |
| 35 | + display_send_data(0x20); // Default value |
| 36 | + display_send_command(0xc6); // FRCTRL2: Frame rate control in normal mode |
| 37 | + display_send_data(0xf); // Default value |
| 38 | + display_send_command(0xd0); // PWCTRL1: Power control 1 |
| 39 | + display_send_data(0xa4); // Set: AVDD 6.8 V, AVCL -4.8 V, VDDS 2.3 V |
| 40 | + display_send_data(0xa1); |
| 41 | + display_send_command(0xe0); // PVGAMCTRL: Positive voltage gamma control |
| 42 | + display_send_data(0xd0); // Set |
| 43 | + display_send_data(0x1); |
| 44 | + display_send_data(0x8); |
| 45 | + display_send_data(0xf); |
| 46 | + display_send_data(0x11); |
| 47 | + display_send_data(0x2a); |
| 48 | + display_send_data(0x36); |
| 49 | + display_send_data(0x55); |
| 50 | + display_send_data(0x44); |
| 51 | + display_send_data(0x3a); |
| 52 | + display_send_data(0xb); |
| 53 | + display_send_data(0x6); |
| 54 | + display_send_data(0x11); |
| 55 | + display_send_data(0x20); |
| 56 | + display_send_command(0xe1); // NVGAMCTRL: Negative voltage gamma control |
| 57 | + display_send_data(0xd0); // Set |
| 58 | + display_send_data(0x2); |
| 59 | + display_send_data(0x7); |
| 60 | + display_send_data(0xa); |
| 61 | + display_send_data(0xb); |
| 62 | + display_send_data(0x18); |
| 63 | + display_send_data(0x34); |
| 64 | + display_send_data(0x43); |
| 65 | + display_send_data(0x4a); |
| 66 | + display_send_data(0x2b); |
| 67 | + display_send_data(0x1b); |
| 68 | + display_send_data(0x1c); |
| 69 | + display_send_data(0x22); |
| 70 | + display_send_data(0x1f); |
| 71 | + display_send_command(0x29); // DISPON: Display on |
| 72 | + display_send_command(0x2c); // RAMWR: Memory write |
73 | 73 |
|
74 | 74 | ## Data write
|
75 | 75 |
|
76 |
| -* display_send_command(0x36); // MADCTL: Memory access control |
77 |
| -* display_send_data(0xa0); |
78 |
| -* display_send_command(0x2a); // CASET: Column address set |
79 |
| -* display_send_data(0x0); // Default (start, end) |
80 |
| -* display_send_data(0x0); |
81 |
| -* display_send_data(0x1); |
82 |
| -* display_send_data(0x3f); |
83 |
| -* display_send_command(0x2b); // RASET: Row address set |
84 |
| -* display_send_data(0x0); // Default (start, end) |
85 |
| -* display_send_data(0x0); |
86 |
| -* display_send_data(0x0); |
87 |
| -* display_send_data(0xef); |
| 76 | + display_send_command(0x36); // MADCTL: Memory access control |
| 77 | + display_send_data(0xa0); |
| 78 | + display_send_command(0x2a); // CASET: Column address set |
| 79 | + display_send_data(0x0); // Default (start, end) |
| 80 | + display_send_data(0x0); |
| 81 | + display_send_data(0x1); |
| 82 | + display_send_data(0x3f); |
| 83 | + display_send_command(0x2b); // RASET: Row address set |
| 84 | + display_send_data(0x0); // Default (start, end) |
| 85 | + display_send_data(0x0); |
| 86 | + display_send_data(0x0); |
| 87 | + display_send_data(0xef); |
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