forked from TinyCC/tinycc
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathx86_64-gen.c
2319 lines (2118 loc) · 64.7 KB
/
x86_64-gen.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* x86-64 code generator for TCC
*
* Copyright (c) 2008 Shinichiro Hamaji
*
* Based on i386-gen.c by Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifdef TARGET_DEFS_ONLY
/* number of available registers */
#define NB_REGS 25
#define NB_ASM_REGS 16
#define CONFIG_TCC_ASM
/* a register can belong to several classes. The classes must be
sorted from more general to more precise (see gv2() code which does
assumptions on it). */
#define RC_INT 0x0001 /* generic integer register */
#define RC_FLOAT 0x0002 /* generic float register */
#define RC_RAX 0x0004
#define RC_RDX 0x0008
#define RC_RCX 0x0010
#define RC_RSI 0x0020
#define RC_RDI 0x0040
#define RC_ST0 0x0080 /* only for long double */
#define RC_R8 0x0100
#define RC_R9 0x0200
#define RC_R10 0x0400
#define RC_R11 0x0800
#define RC_XMM0 0x1000
#define RC_XMM1 0x2000
#define RC_XMM2 0x4000
#define RC_XMM3 0x8000
#define RC_XMM4 0x10000
#define RC_XMM5 0x20000
#define RC_XMM6 0x40000
#define RC_XMM7 0x80000
#define RC_IRET RC_RAX /* function return: integer register */
#define RC_IRE2 RC_RDX /* function return: second integer register */
#define RC_FRET RC_XMM0 /* function return: float register */
#define RC_FRE2 RC_XMM1 /* function return: second float register */
/* pretty names for the registers */
enum {
TREG_RAX = 0,
TREG_RCX = 1,
TREG_RDX = 2,
TREG_RSP = 4,
TREG_RSI = 6,
TREG_RDI = 7,
TREG_R8 = 8,
TREG_R9 = 9,
TREG_R10 = 10,
TREG_R11 = 11,
TREG_XMM0 = 16,
TREG_XMM1 = 17,
TREG_XMM2 = 18,
TREG_XMM3 = 19,
TREG_XMM4 = 20,
TREG_XMM5 = 21,
TREG_XMM6 = 22,
TREG_XMM7 = 23,
TREG_ST0 = 24,
TREG_MEM = 0x20
};
#define REX_BASE(reg) (((reg) >> 3) & 1)
#define REG_VALUE(reg) ((reg) & 7)
/* return registers for function */
#define REG_IRET TREG_RAX /* single word int return register */
#define REG_IRE2 TREG_RDX /* second word return register (for long long) */
#define REG_FRET TREG_XMM0 /* float return register */
#define REG_FRE2 TREG_XMM1 /* second float return register */
/* defined if function parameters must be evaluated in reverse order */
#define INVERT_FUNC_PARAMS
/* pointer size, in bytes */
#define PTR_SIZE 8
/* long double size and alignment, in bytes */
#define LDOUBLE_SIZE 16
#define LDOUBLE_ALIGN 16
/* maximum alignment (for aligned attribute support) */
#define MAX_ALIGN 16
/* define if return values need to be extended explicitely
at caller side (for interfacing with non-TCC compilers) */
#define PROMOTE_RET
#define TCC_TARGET_NATIVE_STRUCT_COPY
ST_FUNC void gen_struct_copy(int size);
/******************************************************/
#else /* ! TARGET_DEFS_ONLY */
/******************************************************/
#define USING_GLOBALS
#include "tcc.h"
#include <assert.h>
ST_DATA const char * const target_machine_defs =
"__x86_64__\0"
"__amd64__\0"
;
ST_DATA const int reg_classes[NB_REGS] = {
/* eax */ RC_INT | RC_RAX,
/* ecx */ RC_INT | RC_RCX,
/* edx */ RC_INT | RC_RDX,
0,
0,
0,
RC_RSI,
RC_RDI,
RC_R8,
RC_R9,
RC_R10,
RC_R11,
0,
0,
0,
0,
/* xmm0 */ RC_FLOAT | RC_XMM0,
/* xmm1 */ RC_FLOAT | RC_XMM1,
/* xmm2 */ RC_FLOAT | RC_XMM2,
/* xmm3 */ RC_FLOAT | RC_XMM3,
/* xmm4 */ RC_FLOAT | RC_XMM4,
/* xmm5 */ RC_FLOAT | RC_XMM5,
/* xmm6 an xmm7 are included so gv() can be used on them,
but they are not tagged with RC_FLOAT because they are
callee saved on Windows */
RC_XMM6,
RC_XMM7,
/* st0 */ RC_ST0
};
static unsigned long func_sub_sp_offset;
static int func_ret_sub;
#if defined(CONFIG_TCC_BCHECK)
static addr_t func_bound_offset;
static unsigned long func_bound_ind;
ST_DATA int func_bound_add_epilog;
#endif
#ifdef TCC_TARGET_PE
static int func_scratch, func_alloca;
#endif
/* XXX: make it faster ? */
ST_FUNC void g(int c)
{
int ind1;
if (nocode_wanted)
return;
ind1 = ind + 1;
if (ind1 > cur_text_section->data_allocated)
section_realloc(cur_text_section, ind1);
cur_text_section->data[ind] = c;
ind = ind1;
}
ST_FUNC void o(unsigned int c)
{
while (c) {
g(c);
c = c >> 8;
}
}
ST_FUNC void gen_le16(int v)
{
g(v);
g(v >> 8);
}
ST_FUNC void gen_le32(int c)
{
g(c);
g(c >> 8);
g(c >> 16);
g(c >> 24);
}
ST_FUNC void gen_le64(int64_t c)
{
g(c);
g(c >> 8);
g(c >> 16);
g(c >> 24);
g(c >> 32);
g(c >> 40);
g(c >> 48);
g(c >> 56);
}
static void orex(int ll, int r, int r2, int b)
{
if ((r & VT_VALMASK) >= VT_CONST)
r = 0;
if ((r2 & VT_VALMASK) >= VT_CONST)
r2 = 0;
if (ll || REX_BASE(r) || REX_BASE(r2))
o(0x40 | REX_BASE(r) | (REX_BASE(r2) << 2) | (ll << 3));
o(b);
}
/* output a symbol and patch all calls to it */
ST_FUNC void gsym_addr(int t, int a)
{
while (t) {
unsigned char *ptr = cur_text_section->data + t;
uint32_t n = read32le(ptr); /* next value */
write32le(ptr, a < 0 ? -a : a - t - 4);
t = n;
}
}
static int is64_type(int t)
{
return ((t & VT_BTYPE) == VT_PTR ||
(t & VT_BTYPE) == VT_FUNC ||
(t & VT_BTYPE) == VT_LLONG);
}
/* instruction + 4 bytes data. Return the address of the data */
static int oad(int c, int s)
{
int t;
if (nocode_wanted)
return s;
o(c);
t = ind;
gen_le32(s);
return t;
}
/* generate jmp to a label */
#define gjmp2(instr,lbl) oad(instr,lbl)
ST_FUNC void gen_addr32(int r, Sym *sym, int c)
{
if (r & VT_SYM)
greloca(cur_text_section, sym, ind, R_X86_64_32S, c), c=0;
gen_le32(c);
}
/* output constant with relocation if 'r & VT_SYM' is true */
ST_FUNC void gen_addr64(int r, Sym *sym, int64_t c)
{
if (r & VT_SYM)
greloca(cur_text_section, sym, ind, R_X86_64_64, c), c=0;
gen_le64(c);
}
/* output constant with relocation if 'r & VT_SYM' is true */
ST_FUNC void gen_addrpc32(int r, Sym *sym, int c)
{
if (r & VT_SYM)
greloca(cur_text_section, sym, ind, R_X86_64_PC32, c-4), c=4;
gen_le32(c-4);
}
/* output got address with relocation */
static void gen_gotpcrel(int r, Sym *sym, int c)
{
#ifdef TCC_TARGET_PE
tcc_error("internal error: no GOT on PE: %s %x %x | %02x %02x %02x\n",
get_tok_str(sym->v, NULL), c, r,
cur_text_section->data[ind-3],
cur_text_section->data[ind-2],
cur_text_section->data[ind-1]
);
#endif
greloca(cur_text_section, sym, ind, R_X86_64_GOTPCREL, -4);
gen_le32(0);
if (c) {
/* we use add c, %xxx for displacement */
orex(1, r, 0, 0x81);
o(0xc0 + REG_VALUE(r));
gen_le32(c);
}
}
static void gen_modrm_impl(int op_reg, int r, Sym *sym, int c, int is_got)
{
op_reg = REG_VALUE(op_reg) << 3;
if ((r & VT_VALMASK) == VT_CONST) {
/* constant memory reference */
if (!(r & VT_SYM)) {
/* Absolute memory reference */
o(0x04 | op_reg); /* [sib] | destreg */
oad(0x25, c); /* disp32 */
} else {
o(0x05 | op_reg); /* (%rip)+disp32 | destreg */
if (is_got) {
gen_gotpcrel(r, sym, c);
} else {
gen_addrpc32(r, sym, c);
}
}
} else if ((r & VT_VALMASK) == VT_LOCAL) {
/* currently, we use only ebp as base */
if (c == (char)c) {
/* short reference */
o(0x45 | op_reg);
g(c);
} else {
oad(0x85 | op_reg, c);
}
} else if ((r & VT_VALMASK) >= TREG_MEM) {
if (c) {
g(0x80 | op_reg | REG_VALUE(r));
gen_le32(c);
} else {
g(0x00 | op_reg | REG_VALUE(r));
}
} else {
g(0x00 | op_reg | REG_VALUE(r));
}
}
/* generate a modrm reference. 'op_reg' contains the additional 3
opcode bits */
static void gen_modrm(int op_reg, int r, Sym *sym, int c)
{
gen_modrm_impl(op_reg, r, sym, c, 0);
}
/* generate a modrm reference. 'op_reg' contains the additional 3
opcode bits */
static void gen_modrm64(int opcode, int op_reg, int r, Sym *sym, int c)
{
int is_got;
is_got = (op_reg & TREG_MEM) && !(sym->type.t & VT_STATIC);
orex(1, r, op_reg, opcode);
gen_modrm_impl(op_reg, r, sym, c, is_got);
}
/* load 'r' from value 'sv' */
void load(int r, SValue *sv)
{
int v, t, ft, fc, fr;
SValue v1;
fr = sv->r;
ft = sv->type.t & ~VT_DEFSIGN;
fc = sv->c.i;
if (fc != sv->c.i && (fr & VT_SYM))
tcc_error("64 bit addend in load");
ft &= ~(VT_VOLATILE | VT_CONSTANT);
#ifndef TCC_TARGET_PE
/* we use indirect access via got */
if ((fr & VT_VALMASK) == VT_CONST && (fr & VT_SYM) &&
(fr & VT_LVAL) && !(sv->sym->type.t & VT_STATIC)) {
/* use the result register as a temporal register */
int tr = r | TREG_MEM;
if (is_float(ft)) {
/* we cannot use float registers as a temporal register */
tr = get_reg(RC_INT) | TREG_MEM;
}
gen_modrm64(0x8b, tr, fr, sv->sym, 0);
/* load from the temporal register */
fr = tr | VT_LVAL;
}
#endif
v = fr & VT_VALMASK;
if (fr & VT_LVAL) {
int b, ll;
if (v == VT_LLOCAL) {
v1.type.t = VT_PTR;
v1.r = VT_LOCAL | VT_LVAL;
v1.c.i = fc;
fr = r;
if (!(reg_classes[fr] & (RC_INT|RC_R11)))
fr = get_reg(RC_INT);
load(fr, &v1);
}
if (fc != sv->c.i) {
/* If the addends doesn't fit into a 32bit signed
we must use a 64bit move. We've checked above
that this doesn't have a sym associated. */
v1.type.t = VT_LLONG;
v1.r = VT_CONST;
v1.c.i = sv->c.i;
fr = r;
if (!(reg_classes[fr] & (RC_INT|RC_R11)))
fr = get_reg(RC_INT);
load(fr, &v1);
fc = 0;
}
ll = 0;
/* Like GCC we can load from small enough properly sized
structs and unions as well.
XXX maybe move to generic operand handling, but should
occur only with asm, so tccasm.c might also be a better place */
if ((ft & VT_BTYPE) == VT_STRUCT) {
int align;
switch (type_size(&sv->type, &align)) {
case 1: ft = VT_BYTE; break;
case 2: ft = VT_SHORT; break;
case 4: ft = VT_INT; break;
case 8: ft = VT_LLONG; break;
default:
tcc_error("invalid aggregate type for register load");
break;
}
}
if ((ft & VT_BTYPE) == VT_FLOAT) {
b = 0x6e0f66;
r = REG_VALUE(r); /* movd */
} else if ((ft & VT_BTYPE) == VT_DOUBLE) {
b = 0x7e0ff3; /* movq */
r = REG_VALUE(r);
} else if ((ft & VT_BTYPE) == VT_LDOUBLE) {
b = 0xdb, r = 5; /* fldt */
} else if ((ft & VT_TYPE) == VT_BYTE || (ft & VT_TYPE) == VT_BOOL) {
b = 0xbe0f; /* movsbl */
} else if ((ft & VT_TYPE) == (VT_BYTE | VT_UNSIGNED)) {
b = 0xb60f; /* movzbl */
} else if ((ft & VT_TYPE) == VT_SHORT) {
b = 0xbf0f; /* movswl */
} else if ((ft & VT_TYPE) == (VT_SHORT | VT_UNSIGNED)) {
b = 0xb70f; /* movzwl */
} else if ((ft & VT_TYPE) == (VT_VOID)) {
/* Can happen with zero size structs */
return;
} else {
assert(((ft & VT_BTYPE) == VT_INT)
|| ((ft & VT_BTYPE) == VT_LLONG)
|| ((ft & VT_BTYPE) == VT_PTR)
|| ((ft & VT_BTYPE) == VT_FUNC)
);
ll = is64_type(ft);
b = 0x8b;
}
if (ll) {
gen_modrm64(b, r, fr, sv->sym, fc);
} else {
orex(ll, fr, r, b);
gen_modrm(r, fr, sv->sym, fc);
}
} else {
if (v == VT_CONST) {
if (fr & VT_SYM) {
#ifdef TCC_TARGET_PE
orex(1,0,r,0x8d);
o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
gen_addrpc32(fr, sv->sym, fc);
#else
if (sv->sym->type.t & VT_STATIC) {
orex(1,0,r,0x8d);
o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
gen_addrpc32(fr, sv->sym, fc);
} else {
orex(1,0,r,0x8b);
o(0x05 + REG_VALUE(r) * 8); /* mov xx(%rip), r */
gen_gotpcrel(r, sv->sym, fc);
}
#endif
} else if (is64_type(ft)) {
if (sv->c.i >> 32) {
orex(1,r,0, 0xb8 + REG_VALUE(r)); /* movabs $xx, r */
gen_le64(sv->c.i);
} else if (sv->c.i > 0) {
orex(0,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
gen_le32(sv->c.i);
} else {
o(0xc031 + REG_VALUE(r) * 0x900); /* xor r, r */
}
} else {
orex(0,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
gen_le32(fc);
}
} else if (v == VT_LOCAL) {
orex(1,0,r,0x8d); /* lea xxx(%ebp), r */
gen_modrm(r, VT_LOCAL, sv->sym, fc);
} else if (v == VT_CMP) {
if (fc & 0x100)
{
v = vtop->cmp_r;
fc &= ~0x100;
/* This was a float compare. If the parity bit is
set the result was unordered, meaning false for everything
except TOK_NE, and true for TOK_NE. */
orex(0, r, 0, 0xb0 + REG_VALUE(r)); /* mov $0/1,%al */
g(v ^ fc ^ (v == TOK_NE));
o(0x037a + (REX_BASE(r) << 8));
}
orex(0,r,0, 0x0f); /* setxx %br */
o(fc);
o(0xc0 + REG_VALUE(r));
orex(0,r,0, 0x0f);
o(0xc0b6 + REG_VALUE(r) * 0x900); /* movzbl %al, %eax */
} else if (v == VT_JMP || v == VT_JMPI) {
t = v & 1;
orex(0,r,0,0);
oad(0xb8 + REG_VALUE(r), t); /* mov $1, r */
o(0x05eb + (REX_BASE(r) << 8)); /* jmp after */
gsym(fc);
orex(0,r,0,0);
oad(0xb8 + REG_VALUE(r), t ^ 1); /* mov $0, r */
} else if (v != r) {
if ((r >= TREG_XMM0) && (r <= TREG_XMM7)) {
if (v == TREG_ST0) {
/* gen_cvt_ftof(VT_DOUBLE); */
o(0xf0245cdd); /* fstpl -0x10(%rsp) */
/* movsd -0x10(%rsp),%xmmN */
o(0x100ff2);
o(0x44 + REG_VALUE(r)*8); /* %xmmN */
o(0xf024);
} else {
assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
if ((ft & VT_BTYPE) == VT_FLOAT) {
o(0x100ff3);
} else {
assert((ft & VT_BTYPE) == VT_DOUBLE);
o(0x100ff2);
}
o(0xc0 + REG_VALUE(v) + REG_VALUE(r)*8);
}
} else if (r == TREG_ST0) {
assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
/* gen_cvt_ftof(VT_LDOUBLE); */
/* movsd %xmmN,-0x10(%rsp) */
o(0x110ff2);
o(0x44 + REG_VALUE(r)*8); /* %xmmN */
o(0xf024);
o(0xf02444dd); /* fldl -0x10(%rsp) */
} else {
orex(is64_type(ft), r, v, 0x89);
o(0xc0 + REG_VALUE(r) + REG_VALUE(v) * 8); /* mov v, r */
}
}
}
}
/* store register 'r' in lvalue 'v' */
void store(int r, SValue *v)
{
int fr, bt, ft, fc;
int op64 = 0;
/* store the REX prefix in this variable when PIC is enabled */
int pic = 0;
fr = v->r & VT_VALMASK;
ft = v->type.t;
fc = v->c.i;
if (fc != v->c.i && (fr & VT_SYM))
tcc_error("64 bit addend in store");
ft &= ~(VT_VOLATILE | VT_CONSTANT);
bt = ft & VT_BTYPE;
#ifndef TCC_TARGET_PE
/* we need to access the variable via got */
if (fr == VT_CONST
&& (v->r & VT_SYM)
&& !(v->sym->type.t & VT_STATIC)) {
/* mov xx(%rip), %r11 */
o(0x1d8b4c);
gen_gotpcrel(TREG_R11, v->sym, v->c.i);
pic = is64_type(bt) ? 0x49 : 0x41;
}
#endif
/* XXX: incorrect if float reg to reg */
if (bt == VT_FLOAT) {
o(0x66);
o(pic);
o(0x7e0f); /* movd */
r = REG_VALUE(r);
} else if (bt == VT_DOUBLE) {
o(0x66);
o(pic);
o(0xd60f); /* movq */
r = REG_VALUE(r);
} else if (bt == VT_LDOUBLE) {
o(0xc0d9); /* fld %st(0) */
o(pic);
o(0xdb); /* fstpt */
r = 7;
} else {
if (bt == VT_SHORT)
o(0x66);
o(pic);
if (bt == VT_BYTE || bt == VT_BOOL)
orex(0, 0, r, 0x88);
else if (is64_type(bt))
op64 = 0x89;
else
orex(0, 0, r, 0x89);
}
if (pic) {
/* xxx r, (%r11) where xxx is mov, movq, fld, or etc */
if (op64)
o(op64);
o(3 + (r << 3));
} else if (op64) {
if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
gen_modrm64(op64, r, v->r, v->sym, fc);
} else if (fr != r) {
orex(1, fr, r, op64);
o(0xc0 + fr + r * 8); /* mov r, fr */
}
} else {
if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
gen_modrm(r, v->r, v->sym, fc);
} else if (fr != r) {
o(0xc0 + fr + r * 8); /* mov r, fr */
}
}
}
/* 'is_jmp' is '1' if it is a jump */
static void gcall_or_jmp(int is_jmp)
{
int r;
if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST &&
((vtop->r & VT_SYM) && (vtop->c.i-4) == (int)(vtop->c.i-4))) {
/* constant symbolic case -> simple relocation */
greloca(cur_text_section, vtop->sym, ind + 1, R_X86_64_PLT32, (int)(vtop->c.i-4));
oad(0xe8 + is_jmp, 0); /* call/jmp im */
} else {
/* otherwise, indirect call */
r = TREG_R11;
load(r, vtop);
o(0x41); /* REX */
o(0xff); /* call/jmp *r */
o(0xd0 + REG_VALUE(r) + (is_jmp << 4));
}
}
#if defined(CONFIG_TCC_BCHECK)
static void gen_bounds_call(int v)
{
Sym *sym = external_helper_sym(v);
oad(0xe8, 0);
greloca(cur_text_section, sym, ind-4, R_X86_64_PLT32, -4);
}
#ifdef TCC_TARGET_PE
# define TREG_FASTCALL_1 TREG_RCX
#else
# define TREG_FASTCALL_1 TREG_RDI
#endif
static void gen_bounds_prolog(void)
{
/* leave some room for bound checking code */
func_bound_offset = lbounds_section->data_offset;
func_bound_ind = ind;
func_bound_add_epilog = 0;
o(0x0d8d48 + ((TREG_FASTCALL_1 == TREG_RDI) * 0x300000)); /*lbound section pointer */
gen_le32 (0);
oad(0xb8, 0); /* call to function */
}
static void gen_bounds_epilog(void)
{
addr_t saved_ind;
addr_t *bounds_ptr;
Sym *sym_data;
int offset_modified = func_bound_offset != lbounds_section->data_offset;
if (!offset_modified && !func_bound_add_epilog)
return;
/* add end of table info */
bounds_ptr = section_ptr_add(lbounds_section, sizeof(addr_t));
*bounds_ptr = 0;
sym_data = get_sym_ref(&char_pointer_type, lbounds_section,
func_bound_offset, PTR_SIZE);
/* generate bound local allocation */
if (offset_modified) {
saved_ind = ind;
ind = func_bound_ind;
greloca(cur_text_section, sym_data, ind + 3, R_X86_64_PC32, -4);
ind = ind + 7;
gen_bounds_call(TOK___bound_local_new);
ind = saved_ind;
}
/* generate bound check local freeing */
o(0x5250); /* save returned value, if any */
o(0x20ec8348); /* sub $32,%rsp */
o(0x290f); /* movaps %xmm0,0x10(%rsp) */
o(0x102444);
o(0x240c290f); /* movaps %xmm1,(%rsp) */
greloca(cur_text_section, sym_data, ind + 3, R_X86_64_PC32, -4);
o(0x0d8d48 + ((TREG_FASTCALL_1 == TREG_RDI) * 0x300000)); /* lea xxx(%rip), %rcx/rdi */
gen_le32 (0);
gen_bounds_call(TOK___bound_local_delete);
o(0x280f); /* movaps 0x10(%rsp),%xmm0 */
o(0x102444);
o(0x240c280f); /* movaps (%rsp),%xmm1 */
o(0x20c48348); /* add $32,%rsp */
o(0x585a); /* restore returned value, if any */
}
#endif
#ifdef TCC_TARGET_PE
#define REGN 4
static const uint8_t arg_regs[REGN] = {
TREG_RCX, TREG_RDX, TREG_R8, TREG_R9
};
/* Prepare arguments in R10 and R11 rather than RCX and RDX
because gv() will not ever use these */
static int arg_prepare_reg(int idx) {
if (idx == 0 || idx == 1)
/* idx=0: r10, idx=1: r11 */
return idx + 10;
else
return idx >= 0 && idx < REGN ? arg_regs[idx] : 0;
}
/* Generate function call. The function address is pushed first, then
all the parameters in call order. This functions pops all the
parameters and the function address. */
static void gen_offs_sp(int b, int r, int d)
{
orex(1,0,r & 0x100 ? 0 : r, b);
if (d == (char)d) {
o(0x2444 | (REG_VALUE(r) << 3));
g(d);
} else {
o(0x2484 | (REG_VALUE(r) << 3));
gen_le32(d);
}
}
static int using_regs(int size)
{
return !(size > 8 || (size & (size - 1)));
}
/* Return the number of registers needed to return the struct, or 0 if
returning via struct pointer. */
ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align, int *regsize)
{
int size, align;
*ret_align = 1; // Never have to re-align return values for x86-64
*regsize = 8;
size = type_size(vt, &align);
if (!using_regs(size))
return 0;
if (size == 8)
ret->t = VT_LLONG;
else if (size == 4)
ret->t = VT_INT;
else if (size == 2)
ret->t = VT_SHORT;
else
ret->t = VT_BYTE;
ret->ref = NULL;
return 1;
}
static int is_sse_float(int t) {
int bt;
bt = t & VT_BTYPE;
return bt == VT_DOUBLE || bt == VT_FLOAT;
}
static int gfunc_arg_size(CType *type) {
int align;
if (type->t & (VT_ARRAY|VT_BITFIELD))
return 8;
return type_size(type, &align);
}
void gfunc_call(int nb_args)
{
int size, r, args_size, i, d, bt, struct_size;
int arg;
#ifdef CONFIG_TCC_BCHECK
if (tcc_state->do_bounds_check)
gbound_args(nb_args);
#endif
args_size = (nb_args < REGN ? REGN : nb_args) * PTR_SIZE;
arg = nb_args;
/* for struct arguments, we need to call memcpy and the function
call breaks register passing arguments we are preparing.
So, we process arguments which will be passed by stack first. */
struct_size = args_size;
for(i = 0; i < nb_args; i++) {
SValue *sv;
--arg;
sv = &vtop[-i];
bt = (sv->type.t & VT_BTYPE);
size = gfunc_arg_size(&sv->type);
if (using_regs(size))
continue; /* arguments smaller than 8 bytes passed in registers or on stack */
if (bt == VT_STRUCT) {
/* align to stack align size */
size = (size + 15) & ~15;
/* generate structure store */
r = get_reg(RC_INT);
gen_offs_sp(0x8d, r, struct_size);
struct_size += size;
/* generate memcpy call */
vset(&sv->type, r | VT_LVAL, 0);
vpushv(sv);
vstore();
--vtop;
} else if (bt == VT_LDOUBLE) {
gv(RC_ST0);
gen_offs_sp(0xdb, 0x107, struct_size);
struct_size += 16;
}
}
if (func_scratch < struct_size)
func_scratch = struct_size;
arg = nb_args;
struct_size = args_size;
for(i = 0; i < nb_args; i++) {
--arg;
bt = (vtop->type.t & VT_BTYPE);
size = gfunc_arg_size(&vtop->type);
if (!using_regs(size)) {
/* align to stack align size */
size = (size + 15) & ~15;
if (arg >= REGN) {
d = get_reg(RC_INT);
gen_offs_sp(0x8d, d, struct_size);
gen_offs_sp(0x89, d, arg*8);
} else {
d = arg_prepare_reg(arg);
gen_offs_sp(0x8d, d, struct_size);
}
struct_size += size;
} else {
if (is_sse_float(vtop->type.t)) {
if (tcc_state->nosse)
tcc_error("SSE disabled");
if (arg >= REGN) {
gv(RC_XMM0);
/* movq %xmm0, j*8(%rsp) */
gen_offs_sp(0xd60f66, 0x100, arg*8);
} else {
/* Load directly to xmmN register */
gv(RC_XMM0 << arg);
d = arg_prepare_reg(arg);
/* mov %xmmN, %rxx */
o(0x66);
orex(1,d,0, 0x7e0f);
o(0xc0 + arg*8 + REG_VALUE(d));
}
} else {
if (bt == VT_STRUCT) {
vtop->type.ref = NULL;
vtop->type.t = size > 4 ? VT_LLONG : size > 2 ? VT_INT
: size > 1 ? VT_SHORT : VT_BYTE;
}
r = gv(RC_INT);
if (arg >= REGN) {
gen_offs_sp(0x89, r, arg*8);
} else {
d = arg_prepare_reg(arg);
orex(1,d,r,0x89); /* mov */
o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
}
}
}
vtop--;
}
save_regs(0);
/* Copy R10 and R11 into RCX and RDX, respectively */
if (nb_args > 0) {
o(0xd1894c); /* mov %r10, %rcx */
if (nb_args > 1) {
o(0xda894c); /* mov %r11, %rdx */
}
}
gcall_or_jmp(0);
if ((vtop->r & VT_SYM) && vtop->sym->v == TOK_alloca) {
/* need to add the "func_scratch" area after alloca */
o(0x48); func_alloca = oad(0x05, func_alloca); /* add $NN, %rax */
#ifdef CONFIG_TCC_BCHECK
if (tcc_state->do_bounds_check)
gen_bounds_call(TOK___bound_alloca_nr); /* new region */
#endif
}
vtop--;
}
#define FUNC_PROLOG_SIZE 11
/* generate function prolog of type 't' */
void gfunc_prolog(Sym *func_sym)
{
CType *func_type = &func_sym->type;
int addr, reg_param_index, bt, size;
Sym *sym;
CType *type;
func_ret_sub = 0;
func_scratch = 32;
func_alloca = 0;
loc = 0;
addr = PTR_SIZE * 2;
ind += FUNC_PROLOG_SIZE;
func_sub_sp_offset = ind;
reg_param_index = 0;
sym = func_type->ref;
/* if the function returns a structure, then add an
implicit pointer parameter */
size = gfunc_arg_size(&func_vt);
if (!using_regs(size)) {
gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
func_vc = addr;
reg_param_index++;
addr += 8;
}
/* define parameters */
while ((sym = sym->next) != NULL) {
type = &sym->type;
bt = type->t & VT_BTYPE;
size = gfunc_arg_size(type);
if (!using_regs(size)) {
if (reg_param_index < REGN) {
gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
}
sym_push(sym->v & ~SYM_FIELD, type,
VT_LLOCAL | VT_LVAL, addr);
} else {
if (reg_param_index < REGN) {
/* save arguments passed by register */
if ((bt == VT_FLOAT) || (bt == VT_DOUBLE)) {
if (tcc_state->nosse)
tcc_error("SSE disabled");
o(0xd60f66); /* movq */
gen_modrm(reg_param_index, VT_LOCAL, NULL, addr);
} else {
gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
}
}
sym_push(sym->v & ~SYM_FIELD, type,
VT_LOCAL | VT_LVAL, addr);
}
addr += 8;
reg_param_index++;
}
while (reg_param_index < REGN) {
if (func_var) {
gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
addr += 8;
}
reg_param_index++;
}