Mastering an STA causes a glitch on SDA

[bobnewgard]

This issue was detected in simulation with commit 4fdaf01.

When mastering a transaction, STA is always generated, per protocol. Upon detecting that STA, the Bit Controller generates a pulse on slave_reset. In the Byte Controller, slave_reset causes the FSM to be reset and cycle through ST_IDLE, resulting in a one-clock glitch on SDA.

Devices with good input filtering will disappear this glitch so in hardware no harm is done, but in a verification environment all sorts of havoc ensues.

I'm flagging this now without a fix identified, but as I build out the verification testbench I may add a test of master → slave → master operation in which a fix can be developed.

[bobnewgard]

A testbench has been created and published at https://codeberg.org/bobn/tb_i2c_herveille_oc. The testbench attains line coverage of 99%.

[gavin5342]

Sorry for the delay. I couldn't think of a good way to show the change by following on from your pull request, so here it is: gavin5342@44856f5. I thought it easier to add here rather than open a new pull request.