diff --git a/RV12/rtl/verilog/core/ex/riscv_bu.sv b/RV12/rtl/verilog/core/ex/riscv_bu.sv index 92a5846..7350173 100644 --- a/RV12/rtl/verilog/core/ex/riscv_bu.sv +++ b/RV12/rtl/verilog/core/ex/riscv_bu.sv @@ -104,13 +104,14 @@ import riscv_state_pkg::*; bp_update; logic [BP_GLOBAL_BITS:0] bp_history; logic [XLEN -1:0] nxt_pc; - - + logic bu_bubble; //////////////////////////////////////////////////////////////// // // Module Body // + + /* * Instruction */ @@ -175,6 +176,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = id_pc_i + ext_immUJ; + bu_bubble = 1'b0; end {1'b0,JALR }: if (has_rsb) begin @@ -186,6 +188,7 @@ import riscv_state_pkg::*; dc_clean = 'b0; nxt_pc = (opA_i + opB_i) & { {XLEN-1{1'b1}},1'b0 }; + bu_bubble = 1'b0; pipeflush = is_ret ? (nxt_pc[XLEN-1:1] != id_rsb_pc_i[XLEN-1:1]) : 1'b1; end else @@ -198,6 +201,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = (opA_i + opB_i) & { {XLEN-1{1'b1}},1'b0 }; + bu_bubble = 1'b0; end {1'b0,BEQ }: begin btaken = (opA_i == opB_i); @@ -208,6 +212,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i +(is_16bit_instruction ? 'h2 : 'h4); + bu_bubble = 1'b0; end {1'b0,BNE }: begin btaken = (opA_i != opB_i); @@ -218,6 +223,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + (is_16bit_instruction ? 'h2 : 'h4); + bu_bubble = 1'b0; end {1'b0,BLTU }: begin btaken = (opA_i < opB_i); @@ -228,6 +234,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4; + bu_bubble = 1'b0; end {1'b0,BGEU }: begin btaken = (opA_i >= opB_i); @@ -238,6 +245,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i +'h4; + bu_bubble = 1'b0; end {1'b0,BLT }: begin btaken = $signed(opA_i) < $signed(opB_i); @@ -248,6 +256,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4; + bu_bubble = 1'b0; end {1'b0,BGE }: begin btaken = $signed(opA_i) >= $signed(opB_i); @@ -258,6 +267,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = btaken ? id_pc_i + ext_immSB : id_pc_i + 'h4; + bu_bubble = 1'b0; end {1'b0,MISCMEM}: case (id_insn_i.instr) FENCE_I: begin @@ -269,7 +279,8 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b1; nxt_pc = id_pc_i +'h4; - end + bu_bubble = 1'b0; + end default: begin btaken = 'b0; bp_update = 'b0; @@ -279,7 +290,8 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = id_pc_i + 'h4; - end + bu_bubble = 1'b1; + end endcase default : begin btaken = 'b0; @@ -290,6 +302,7 @@ import riscv_state_pkg::*; dc_invalidate = 'b0; dc_clean = 'b0; nxt_pc = id_pc_i + (is_16bit_instruction ? 'h2 : 'h4); + bu_bubble = 1'b1; end endcase diff --git a/RV12/rtl/verilog/core/riscv_ex.sv b/RV12/rtl/verilog/core/riscv_ex.sv index b89b65b..3ac0546 100644 --- a/RV12/rtl/verilog/core/riscv_ex.sv +++ b/RV12/rtl/verilog/core/riscv_ex.sv @@ -142,11 +142,33 @@ import biu_constants_pkg::*; logic [EXCEPTION_SIZE-1:0] bu_exception; interrupts_exceptions_t lsu_exceptions; + // For inst retired + logic bu_bubble_exe; + logic bu_bubble_id; + opcR_t opcR; + always @(posedge clk_i, negedge rst_ni) + if (!rst_ni ) bu_bubble_exe <= 1'b1; + else if ( ex_exceptions_o.any || + mem_exceptions_i.any || + wb_exceptions_i.any ) bu_bubble_exe <= 1'b1; + else if (!ex_stall_o ) bu_bubble_exe <= bu_bubble_id | id_insn_i.bubble; + + assign opcR = decode_opcR(id_insn_i.instr); + + always_comb begin + if(opcR.opcode inside {JAL, JALR, BEQ, BNE, BLTU, BGEU, BLT, BGE}) + bu_bubble_id = 1'b0; + else if(id_insn_i.instr inside{FENCE_I, FENCE, ECALL, EBREAK}) + bu_bubble_id = 1'b0; + else + bu_bubble_id = 1'b1; // inst doesn't take effect on branch unit + end + //////////////////////////////////////////////////////////////// // // Module Body - // + // /* * Program Counter @@ -293,7 +315,6 @@ import biu_constants_pkg::*; .mem_exceptions_i ( mem_exceptions_i ), .wb_exceptions_i ( wb_exceptions_i ), .bu_exceptions_o ( ex_exceptions_o ), - .opA_i ( opA ), .opB_i ( opB ) ); @@ -361,6 +382,7 @@ endgenerate */ assign ex_insn_o.bubble = alu_bubble & lsu_bubble & mul_bubble & div_bubble; + assign ex_insn_o.retired = ~(alu_bubble & lsu_bubble & bu_bubble_exe & mul_bubble & div_bubble); assign ex_stall_o = mem_stall_i | lsu_stall | mul_stall | div_stall; //result diff --git a/RV12/rtl/verilog/core/riscv_mem.sv b/RV12/rtl/verilog/core/riscv_mem.sv index d2fe1df..9ca1d42 100644 --- a/RV12/rtl/verilog/core/riscv_mem.sv +++ b/RV12/rtl/verilog/core/riscv_mem.sv @@ -25,7 +25,7 @@ // See the License for permissions and limitations under the // // License. // // // -///////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////// module riscv_mem @@ -69,6 +69,13 @@ import riscv_state_pkg::*; // Module Body // + // inst retired + + always @(posedge clk_i, negedge rst_ni) + if (!rst_ni ) mem_insn_o.retired <= 'h0; + else if ( mem_exceptions_up_i.any) mem_insn_o.retired <= 'h0; + else if (!mem_stall_i ) mem_insn_o.retired <= mem_insn_i.retired; + /* * Program Counter */ diff --git a/RV12/rtl/verilog/core/riscv_state1.10.sv b/RV12/rtl/verilog/core/riscv_state1.10.sv index 996c392..36c6610 100644 --- a/RV12/rtl/verilog/core/riscv_state1.10.sv +++ b/RV12/rtl/verilog/core/riscv_state1.10.sv @@ -797,8 +797,10 @@ generate else if ( (ex_csr_we_i && ex_csr_reg_i == MINSTRETH && st_prv_o == PRV_M) || (du_we_csr_i && du_addr_i == MINSTRETH) ) csr.minstret.h <= csr_wval; - else if (!wb_insn_i.bubble) - csr.minstret <= csr.minstret + 'h1; + else + csr.minstret <= csr.minstret + wb_insn_i.retired; + // else if (!wb_insn_i.bubble) + // csr.minstret <= csr.minstret + 'h1; end end else //(XLEN > 32) diff --git a/RV12/rtl/verilog/core/riscv_wb.sv b/RV12/rtl/verilog/core/riscv_wb.sv index 9b6a31c..6676cfe 100644 --- a/RV12/rtl/verilog/core/riscv_wb.sv +++ b/RV12/rtl/verilog/core/riscv_wb.sv @@ -95,6 +95,13 @@ import riscv_state_pkg::*; // Module Body // + + always @(posedge clk_i, negedge rst_ni) + if (!rst_ni ) wb_insn_o.retired <= 'h0; + else if ( wb_exceptions_o.any) wb_insn_o.retired <= 'h0; + else if ( wb_stall_o ) wb_insn_o.retired <= 'h0; + else wb_insn_o.retired <= mem_insn_i.retired; + /* * Program Counter */