.synopsys_dc.setup

#   1. Modify this file to fit your own environment
#   2. Copy this file synopsys_dc.setup to .synopsys_dc.setup 
#      and put it in tool's invoking directory or your home directory.
#   set search_path      "/usr/cad/library/CBDK_TSMC90GUTM_Arm_f1.0/CIC/SynopsysDC/db/ $search_path"
#   set search_path      "/usr/cad/library/CBDK_IC_Contest_v2.1/SynopsysDC/db/ $search_path"


set company "CIC"
set designer "Student"
set search_path      "/usr/cad/library/CBDK_IC_Contest_v2.5/SynopsysDC/db/ $search_path"
set link_library     "* slow.db fast.db dw_foundation.sldb"
set target_library   " slow.db fast.db"
set symbol_library   " generic.sdb"
set synthetic_library "dw_foundation.sldb"


set hdlin_translate_off_skip_text "TRUE"
set edifout_netlist_only "TRUE"
set verilogout_no_tri true
set plot_command {lpr -Plp}

set sh_enable_line_editing true
set sh_line_editing_mode emacs
history keep 100
alias h history

set bus_inference_style {%s[%d]}
set bus_naming_style {%s[%d]}
set hdlout_internal_busses true
define_name_rules name_rule -allowed {a-z A-Z 0-9 _} -max_length 255 -type cell
define_name_rules name_rule -allowed {a-z A-Z 0-9 _[]} -max_length 255 -type net
define_name_rules name_rule -map {{"\\*cell\\*" "cell"}}
define_name_rules name_rule -case_insensitive

set view_script_submenu_items [list {Avoid assign statement} {set_fix_multiple_port_nets -all -buffer_constant} {Change Naming Rule} {change_names -rule verilog -hierarchy} {Write SDF} {write_sdf -version 1.0 -context verilog chip.sdf}]