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dhalbertdhalbert
authored
Merge pull request #9974 from snkYmkrct/main
Adding Daisy Seed stm32H750 board - initial support
2 parents 1f8d00e + fe55cb7 commit 82caf90

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22 files changed

+1092
-14
lines changed

22 files changed

+1092
-14
lines changed

‎ports/stm/Makefile

+3-3
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ CFLAGS += -DSTM32_HAL_H="<stm32$(MCU_SERIES_LOWER)xx_hal.h>"
7373
CFLAGS += -DSTM32_SERIES_LOWER='"stm32$(MCU_SERIES_LOWER)"'
7474

7575
# Floating point settings
76-
ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx))
76+
ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx STM32H750xx))
7777
CFLAGS += -mfpu=fpv5-d16 -mfloat-abi=hard
7878
else
7979
CFLAGS += -mfpu=fpv4-sp-d16 -mfloat-abi=hard
@@ -165,7 +165,7 @@ endif
165165

166166
# Need this to avoid UART linker problems. TODO: rewrite to use registered callbacks.
167167
# Does not exist for F4 and lower
168-
ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx STM32L4R5xx))
168+
ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32F765xx STM32F767xx STM32F769xx STM32H743xx STM32H750xx STM32L4R5xx))
169169
SRC_STM32 += $(HAL_DIR)/Src/stm32$(MCU_SERIES_LOWER)xx_hal_uart_ex.c
170170
endif
171171

@@ -240,7 +240,7 @@ SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_MOD) $(SRC_COMMON_HAL_EXPANDED) $(S
240240
SRC_QSTR_PREPROCESSOR +=
241241

242242
# Bin section settings specific to the STM32H7
243-
ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32H743xx))
243+
ifeq ($(MCU_VARIANT),$(filter $(MCU_VARIANT),STM32H743xx STM32H750xx))
244244
MCU_SECTIONS = -j .isr_vector -j .text -j .data -j .itcm -j .dtcm_data $^ $@
245245
else
246246
MCU_SECTIONS = $^ $@

‎ports/stm/boards/STM32H750.ld

+34
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
/*
2+
GNU linker script for STM32H750
3+
*/
4+
5+
/* Entry Point */
6+
ENTRY(Reset_Handler)
7+
8+
_ld_default_stack_size = 24K;
9+
10+
/* Specify the memory areas -- CircuitPython is loaded on the external QSPI flash */
11+
MEMORY
12+
{
13+
FLASH (rx) : ORIGIN = 0x90000000, LENGTH = 8M /* 8M */
14+
FLASH_ISR (rx) : ORIGIN = 0x90000000, LENGTH = 4K /* sector 0 */
15+
FLASH_FIRMWARE (rx) : ORIGIN = 0x90001000, LENGTH = 8M-4K
16+
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
17+
RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM */
18+
SRAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K /* AHB1 SRAM */
19+
SRAM_D3 (xrw) : ORIGIN = 0x30040000, LENGTH = 64K /* AHB2 SRAM */
20+
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
21+
}
22+
23+
/* produce a link error if there is not this amount of RAM for these sections */
24+
_minimum_stack_size = 24K; /*TODO: this can probably be bigger, but how big?*/
25+
_minimum_heap_size = 16K;
26+
27+
/* Define tho top end of the stack. The stack is full descending so begins just
28+
above last byte of RAM. Note that EABI requires the stack to be 8-byte
29+
aligned for a call. */
30+
_estack = ORIGIN(DTCM) + LENGTH(DTCM);
31+
32+
/* RAM extents for the garbage collector */
33+
_ram_start = ORIGIN(RAM);
34+
_ram_end = ORIGIN(RAM) + LENGTH(RAM);

‎ports/stm/boards/common_tcm.ld

+10
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,16 @@ SECTIONS
134134
} > DTCM
135135
_ld_stack_top = ORIGIN(DTCM) + LENGTH(DTCM);
136136

137+
.ARM.extab :
138+
{
139+
*(.ARM.extab* .gnu.linkonce.armextab.*)
140+
} >FLASH_FIRMWARE
141+
.ARM :
142+
{
143+
__exidx_start = .;
144+
*(.ARM.exidx*)
145+
__exidx_end = .;
146+
} >FLASH_FIRMWARE
137147

138148
.ARM.attributes 0 : { *(.ARM.attributes) }
139149
}

‎ports/stm/boards/daisy_seed_with_sdram/board.c

+9
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
// This file is part of the CircuitPython project: https://circuitpython.org
2+
//
3+
// SPDX-FileCopyrightText: Copyright (c) 2024 snkYmkrct
4+
//
5+
// SPDX-License-Identifier: MIT
6+
7+
#include "supervisor/board.h"
8+
9+
// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.

‎ports/stm/boards/daisy_seed_with_sdram/mpconfigboard.h

+33
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
// This file is part of the CircuitPython project: https://circuitpython.org
2+
//
3+
// SPDX-FileCopyrightText: Copyright (c) 2024 snkYmkrct
4+
//
5+
// SPDX-License-Identifier: MIT
6+
7+
// Micropython setup
8+
9+
#define MICROPY_HW_BOARD_NAME "DAISY_SEED"
10+
#define MICROPY_HW_MCU_NAME "STM32H750xx"
11+
12+
#define MICROPY_HW_LED_STATUS (&pin_PC07)
13+
14+
// H7 and F7 MPU definitions
15+
#define CPY_FLASH_REGION_SIZE ARM_MPU_REGION_SIZE_8MB
16+
#define CPY_ITCM_REGION_SIZE ARM_MPU_REGION_SIZE_64KB
17+
#define CPY_DTCM_REGION_SIZE ARM_MPU_REGION_SIZE_128KB
18+
#define CPY_SRAM_REGION_SIZE ARM_MPU_REGION_SIZE_512KB
19+
#define CPY_SRAM_SUBMASK 0x00
20+
#define CPY_SRAM_START_ADDR 0x24000000
21+
22+
#define HSE_VALUE ((uint32_t)16000000)
23+
#define BOARD_HSE_SOURCE (RCC_HSE_ON) // use external oscillator
24+
#define BOARD_HAS_LOW_SPEED_CRYSTAL (0)
25+
26+
#define CIRCUITPY_CONSOLE_UART_TX (&pin_PB09)
27+
#define CIRCUITPY_CONSOLE_UART_RX (&pin_PB08)
28+
29+
// USB
30+
#define BOARD_NO_USB_OTG_ID_SENSE (1)
31+
32+
// for RNG not audio
33+
#define CPY_CLK_USB_USES_AUDIOPLL (1)

‎ports/stm/boards/daisy_seed_with_sdram/mpconfigboard.mk

+14
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
USB_VID = 0x0483
2+
USB_PID = 0x5740
3+
USB_PRODUCT = "Daisy Seed"
4+
USB_MANUFACTURER = "STMicroelectronics"
5+
6+
# Small FS created on half of the internal flash -- other half is reserved for the H750 bootloader
7+
INTERNAL_FLASH_FILESYSTEM = 1
8+
9+
MCU_SERIES = H7
10+
MCU_VARIANT = STM32H750xx
11+
MCU_PACKAGE = UFBGA176
12+
13+
LD_COMMON = boards/common_tcm.ld
14+
LD_FILE = boards/STM32H750.ld

‎ports/stm/boards/daisy_seed_with_sdram/pins.c

+13
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
// This file is part of the CircuitPython project: https://circuitpython.org
2+
//
3+
// SPDX-FileCopyrightText: Copyright (c) 2024 snkYmkrct
4+
//
5+
// SPDX-License-Identifier: MIT
6+
7+
#include "shared-bindings/board/__init__.h"
8+
9+
static const mp_rom_map_elem_t board_module_globals_table[] = {
10+
{MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_PC07)},
11+
{MP_ROM_QSTR(MP_QSTR_BOOT), MP_ROM_PTR(&pin_PG03)},
12+
};
13+
MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);

‎ports/stm/common-hal/microcontroller/Pin.c

+2
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@
1111

1212
#if defined(TFBGA216)
1313
GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI, GPIOJ, GPIOK};
14+
#elif defined(UFBGA176)
15+
GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI};
1416
#elif defined(LQFP144) || defined(WLCSP144)
1517
GPIO_TypeDef *ports[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG};
1618
#elif defined(LQFP100_f4) || (LQFP100_x7)

‎ports/stm/packages/UFBGA176.c

+183
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,183 @@
1+
// This file is part of the CircuitPython project: https://circuitpython.org
2+
//
3+
// SPDX-FileCopyrightText: Copyright (c) 2024 snkYmkrct
4+
//
5+
// SPDX-License-Identifier: MIT
6+
7+
#include "shared-bindings/microcontroller/__init__.h"
8+
#include "common-hal/microcontroller/Pin.h"
9+
#include "py/obj.h"
10+
11+
static const mp_rom_map_elem_t mcu_pin_globals_table[] = {
12+
// Row A
13+
{ MP_ROM_QSTR(MP_QSTR_PE03), MP_ROM_PTR(&pin_PE03) },
14+
{ MP_ROM_QSTR(MP_QSTR_PE02), MP_ROM_PTR(&pin_PE02) },
15+
{ MP_ROM_QSTR(MP_QSTR_PE01), MP_ROM_PTR(&pin_PE01) },
16+
{ MP_ROM_QSTR(MP_QSTR_PE00), MP_ROM_PTR(&pin_PE00) },
17+
{ MP_ROM_QSTR(MP_QSTR_PB08), MP_ROM_PTR(&pin_PB08) },
18+
{ MP_ROM_QSTR(MP_QSTR_PB05), MP_ROM_PTR(&pin_PB05) },
19+
{ MP_ROM_QSTR(MP_QSTR_PG14), MP_ROM_PTR(&pin_PG14) },
20+
{ MP_ROM_QSTR(MP_QSTR_PG13), MP_ROM_PTR(&pin_PG13) },
21+
{ MP_ROM_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },
22+
{ MP_ROM_QSTR(MP_QSTR_PB03), MP_ROM_PTR(&pin_PB03) },
23+
{ MP_ROM_QSTR(MP_QSTR_PD07), MP_ROM_PTR(&pin_PD07) },
24+
{ MP_ROM_QSTR(MP_QSTR_PC12), MP_ROM_PTR(&pin_PC12) },
25+
{ MP_ROM_QSTR(MP_QSTR_PA15), MP_ROM_PTR(&pin_PA15) },
26+
{ MP_ROM_QSTR(MP_QSTR_PA14), MP_ROM_PTR(&pin_PA14) },
27+
{ MP_ROM_QSTR(MP_QSTR_PA13), MP_ROM_PTR(&pin_PA13) },
28+
29+
// Row B
30+
{ MP_ROM_QSTR(MP_QSTR_PE04), MP_ROM_PTR(&pin_PE04) },
31+
{ MP_ROM_QSTR(MP_QSTR_PE05), MP_ROM_PTR(&pin_PE05) },
32+
{ MP_ROM_QSTR(MP_QSTR_PE06), MP_ROM_PTR(&pin_PE06) },
33+
{ MP_ROM_QSTR(MP_QSTR_PB09), MP_ROM_PTR(&pin_PB09) },
34+
{ MP_ROM_QSTR(MP_QSTR_PB07), MP_ROM_PTR(&pin_PB07) },
35+
{ MP_ROM_QSTR(MP_QSTR_PB06), MP_ROM_PTR(&pin_PB06) },
36+
{ MP_ROM_QSTR(MP_QSTR_PG15), MP_ROM_PTR(&pin_PG15) },
37+
{ MP_ROM_QSTR(MP_QSTR_PG12), MP_ROM_PTR(&pin_PG12) },
38+
{ MP_ROM_QSTR(MP_QSTR_PG11), MP_ROM_PTR(&pin_PG11) },
39+
{ MP_ROM_QSTR(MP_QSTR_PG10), MP_ROM_PTR(&pin_PG10) },
40+
{ MP_ROM_QSTR(MP_QSTR_PD06), MP_ROM_PTR(&pin_PD06) },
41+
{ MP_ROM_QSTR(MP_QSTR_PD00), MP_ROM_PTR(&pin_PD00) },
42+
{ MP_ROM_QSTR(MP_QSTR_PC11), MP_ROM_PTR(&pin_PC11) },
43+
{ MP_ROM_QSTR(MP_QSTR_PC10), MP_ROM_PTR(&pin_PC10) },
44+
{ MP_ROM_QSTR(MP_QSTR_PA12), MP_ROM_PTR(&pin_PA12) },
45+
46+
// Row C
47+
{ MP_ROM_QSTR(MP_QSTR_PI07), MP_ROM_PTR(&pin_PI07) },
48+
{ MP_ROM_QSTR(MP_QSTR_PI06), MP_ROM_PTR(&pin_PI06) },
49+
{ MP_ROM_QSTR(MP_QSTR_PI05), MP_ROM_PTR(&pin_PI05) },
50+
{ MP_ROM_QSTR(MP_QSTR_PG09), MP_ROM_PTR(&pin_PG09) },
51+
{ MP_ROM_QSTR(MP_QSTR_PD05), MP_ROM_PTR(&pin_PD05) },
52+
{ MP_ROM_QSTR(MP_QSTR_PD01), MP_ROM_PTR(&pin_PD01) },
53+
{ MP_ROM_QSTR(MP_QSTR_PI03), MP_ROM_PTR(&pin_PI03) },
54+
{ MP_ROM_QSTR(MP_QSTR_PI02), MP_ROM_PTR(&pin_PI02) },
55+
{ MP_ROM_QSTR(MP_QSTR_PA11), MP_ROM_PTR(&pin_PA11) },
56+
57+
// Row D
58+
{ MP_ROM_QSTR(MP_QSTR_PC13), MP_ROM_PTR(&pin_PC13) },
59+
{ MP_ROM_QSTR(MP_QSTR_PI08), MP_ROM_PTR(&pin_PI08) },
60+
{ MP_ROM_QSTR(MP_QSTR_PI09), MP_ROM_PTR(&pin_PI09) },
61+
{ MP_ROM_QSTR(MP_QSTR_PI04), MP_ROM_PTR(&pin_PI04) },
62+
{ MP_ROM_QSTR(MP_QSTR_PD04), MP_ROM_PTR(&pin_PD04) },
63+
{ MP_ROM_QSTR(MP_QSTR_PD03), MP_ROM_PTR(&pin_PD03) },
64+
{ MP_ROM_QSTR(MP_QSTR_PD02), MP_ROM_PTR(&pin_PD02) },
65+
{ MP_ROM_QSTR(MP_QSTR_PH15), MP_ROM_PTR(&pin_PH15) },
66+
{ MP_ROM_QSTR(MP_QSTR_PI01), MP_ROM_PTR(&pin_PI01) },
67+
{ MP_ROM_QSTR(MP_QSTR_PA10), MP_ROM_PTR(&pin_PA10) },
68+
69+
// Row E
70+
// { MP_ROM_QSTR(MP_QSTR_PC14), MP_ROM_PTR(&pin_PC14) },
71+
{ MP_ROM_QSTR(MP_QSTR_PF00), MP_ROM_PTR(&pin_PF00) },
72+
{ MP_ROM_QSTR(MP_QSTR_PI10), MP_ROM_PTR(&pin_PI10) },
73+
{ MP_ROM_QSTR(MP_QSTR_PI11), MP_ROM_PTR(&pin_PI11) },
74+
{ MP_ROM_QSTR(MP_QSTR_PH13), MP_ROM_PTR(&pin_PH13) },
75+
{ MP_ROM_QSTR(MP_QSTR_PH14), MP_ROM_PTR(&pin_PH14) },
76+
{ MP_ROM_QSTR(MP_QSTR_PI00), MP_ROM_PTR(&pin_PI00) },
77+
{ MP_ROM_QSTR(MP_QSTR_PA09), MP_ROM_PTR(&pin_PA09) },
78+
79+
// Row F
80+
// { MP_ROM_QSTR(MP_QSTR_PC15), MP_ROM_PTR(&pin_PC15) },
81+
{ MP_ROM_QSTR(MP_QSTR_PH02), MP_ROM_PTR(&pin_PH02) },
82+
{ MP_ROM_QSTR(MP_QSTR_PC09), MP_ROM_PTR(&pin_PC09) },
83+
{ MP_ROM_QSTR(MP_QSTR_PA08), MP_ROM_PTR(&pin_PA08) },
84+
85+
// Row G
86+
// { MP_ROM_QSTR(MP_QSTR_PH00), MP_ROM_PTR(&pin_PH00) },
87+
{ MP_ROM_QSTR(MP_QSTR_PH03), MP_ROM_PTR(&pin_PH03) },
88+
{ MP_ROM_QSTR(MP_QSTR_PC08), MP_ROM_PTR(&pin_PC08) },
89+
{ MP_ROM_QSTR(MP_QSTR_PC07), MP_ROM_PTR(&pin_PC07) },
90+
91+
// Row H
92+
// { MP_ROM_QSTR(MP_QSTR_PH01), MP_ROM_PTR(&pin_PH01) },
93+
{ MP_ROM_QSTR(MP_QSTR_PF02), MP_ROM_PTR(&pin_PF02) },
94+
{ MP_ROM_QSTR(MP_QSTR_PF01), MP_ROM_PTR(&pin_PF01) },
95+
{ MP_ROM_QSTR(MP_QSTR_PH04), MP_ROM_PTR(&pin_PH04) },
96+
{ MP_ROM_QSTR(MP_QSTR_PG08), MP_ROM_PTR(&pin_PG08) },
97+
{ MP_ROM_QSTR(MP_QSTR_PC06), MP_ROM_PTR(&pin_PC06) },
98+
99+
// Row J
100+
{ MP_ROM_QSTR(MP_QSTR_PF03), MP_ROM_PTR(&pin_PF03) },
101+
{ MP_ROM_QSTR(MP_QSTR_PF04), MP_ROM_PTR(&pin_PF04) },
102+
{ MP_ROM_QSTR(MP_QSTR_PH05), MP_ROM_PTR(&pin_PH05) },
103+
{ MP_ROM_QSTR(MP_QSTR_PG07), MP_ROM_PTR(&pin_PG07) },
104+
{ MP_ROM_QSTR(MP_QSTR_PG06), MP_ROM_PTR(&pin_PG06) },
105+
106+
// Row K
107+
{ MP_ROM_QSTR(MP_QSTR_PF07), MP_ROM_PTR(&pin_PF07) },
108+
{ MP_ROM_QSTR(MP_QSTR_PF06), MP_ROM_PTR(&pin_PF06) },
109+
{ MP_ROM_QSTR(MP_QSTR_PF05), MP_ROM_PTR(&pin_PF05) },
110+
{ MP_ROM_QSTR(MP_QSTR_PH12), MP_ROM_PTR(&pin_PH12) },
111+
{ MP_ROM_QSTR(MP_QSTR_PG05), MP_ROM_PTR(&pin_PG05) },
112+
{ MP_ROM_QSTR(MP_QSTR_PG04), MP_ROM_PTR(&pin_PG04) },
113+
{ MP_ROM_QSTR(MP_QSTR_PG03), MP_ROM_PTR(&pin_PG03) },
114+
115+
// Row L
116+
{ MP_ROM_QSTR(MP_QSTR_PF10), MP_ROM_PTR(&pin_PF10) },
117+
{ MP_ROM_QSTR(MP_QSTR_PF09), MP_ROM_PTR(&pin_PF09) },
118+
{ MP_ROM_QSTR(MP_QSTR_PF08), MP_ROM_PTR(&pin_PF08) },
119+
{ MP_ROM_QSTR(MP_QSTR_PH11), MP_ROM_PTR(&pin_PH11) },
120+
{ MP_ROM_QSTR(MP_QSTR_PH10), MP_ROM_PTR(&pin_PH10) },
121+
{ MP_ROM_QSTR(MP_QSTR_PD15), MP_ROM_PTR(&pin_PD15) },
122+
{ MP_ROM_QSTR(MP_QSTR_PG02), MP_ROM_PTR(&pin_PG02) },
123+
124+
// Row M
125+
{ MP_ROM_QSTR(MP_QSTR_PC00), MP_ROM_PTR(&pin_PC00) },
126+
{ MP_ROM_QSTR(MP_QSTR_PC01), MP_ROM_PTR(&pin_PC01) },
127+
// { MP_ROM_QSTR(MP_QSTR_PC02C), MP_ROM_PTR(&pin_PC02C) },
128+
// { MP_ROM_QSTR(MP_QSTR_PC03C), MP_ROM_PTR(&pin_PC03C) },
129+
{ MP_ROM_QSTR(MP_QSTR_PB02), MP_ROM_PTR(&pin_PB02) },
130+
{ MP_ROM_QSTR(MP_QSTR_PG01), MP_ROM_PTR(&pin_PG01) },
131+
{ MP_ROM_QSTR(MP_QSTR_PH06), MP_ROM_PTR(&pin_PH06) },
132+
{ MP_ROM_QSTR(MP_QSTR_PH08), MP_ROM_PTR(&pin_PH08) },
133+
{ MP_ROM_QSTR(MP_QSTR_PH09), MP_ROM_PTR(&pin_PH09) },
134+
{ MP_ROM_QSTR(MP_QSTR_PD14), MP_ROM_PTR(&pin_PD14) },
135+
{ MP_ROM_QSTR(MP_QSTR_PD13), MP_ROM_PTR(&pin_PD13) },
136+
137+
// Row N
138+
{ MP_ROM_QSTR(MP_QSTR_PA01), MP_ROM_PTR(&pin_PA01) },
139+
{ MP_ROM_QSTR(MP_QSTR_PA00), MP_ROM_PTR(&pin_PA00) },
140+
{ MP_ROM_QSTR(MP_QSTR_PA04), MP_ROM_PTR(&pin_PA04) },
141+
{ MP_ROM_QSTR(MP_QSTR_PC04), MP_ROM_PTR(&pin_PC04) },
142+
{ MP_ROM_QSTR(MP_QSTR_PF13), MP_ROM_PTR(&pin_PF13) },
143+
{ MP_ROM_QSTR(MP_QSTR_PG00), MP_ROM_PTR(&pin_PG00) },
144+
{ MP_ROM_QSTR(MP_QSTR_PE13), MP_ROM_PTR(&pin_PE13) },
145+
{ MP_ROM_QSTR(MP_QSTR_PH07), MP_ROM_PTR(&pin_PH07) },
146+
{ MP_ROM_QSTR(MP_QSTR_PD12), MP_ROM_PTR(&pin_PD12) },
147+
{ MP_ROM_QSTR(MP_QSTR_PD11), MP_ROM_PTR(&pin_PD11) },
148+
{ MP_ROM_QSTR(MP_QSTR_PD10), MP_ROM_PTR(&pin_PD10) },
149+
150+
// Row P
151+
{ MP_ROM_QSTR(MP_QSTR_PA02), MP_ROM_PTR(&pin_PA02) },
152+
{ MP_ROM_QSTR(MP_QSTR_PA06), MP_ROM_PTR(&pin_PA06) },
153+
{ MP_ROM_QSTR(MP_QSTR_PA05), MP_ROM_PTR(&pin_PA05) },
154+
{ MP_ROM_QSTR(MP_QSTR_PC05), MP_ROM_PTR(&pin_PC05) },
155+
{ MP_ROM_QSTR(MP_QSTR_PF12), MP_ROM_PTR(&pin_PF12) },
156+
{ MP_ROM_QSTR(MP_QSTR_PF15), MP_ROM_PTR(&pin_PF15) },
157+
{ MP_ROM_QSTR(MP_QSTR_PE08), MP_ROM_PTR(&pin_PE08) },
158+
{ MP_ROM_QSTR(MP_QSTR_PE09), MP_ROM_PTR(&pin_PE09) },
159+
{ MP_ROM_QSTR(MP_QSTR_PE11), MP_ROM_PTR(&pin_PE11) },
160+
{ MP_ROM_QSTR(MP_QSTR_PE14), MP_ROM_PTR(&pin_PE14) },
161+
{ MP_ROM_QSTR(MP_QSTR_PB12), MP_ROM_PTR(&pin_PB12) },
162+
{ MP_ROM_QSTR(MP_QSTR_PB13), MP_ROM_PTR(&pin_PB13) },
163+
{ MP_ROM_QSTR(MP_QSTR_PD09), MP_ROM_PTR(&pin_PD09) },
164+
{ MP_ROM_QSTR(MP_QSTR_PD08), MP_ROM_PTR(&pin_PD08) },
165+
166+
// Row R
167+
{ MP_ROM_QSTR(MP_QSTR_PA03), MP_ROM_PTR(&pin_PA03) },
168+
{ MP_ROM_QSTR(MP_QSTR_PA07), MP_ROM_PTR(&pin_PA07) },
169+
{ MP_ROM_QSTR(MP_QSTR_PB01), MP_ROM_PTR(&pin_PB01) },
170+
{ MP_ROM_QSTR(MP_QSTR_PB00), MP_ROM_PTR(&pin_PB00) },
171+
{ MP_ROM_QSTR(MP_QSTR_PF11), MP_ROM_PTR(&pin_PF11) },
172+
{ MP_ROM_QSTR(MP_QSTR_PF14), MP_ROM_PTR(&pin_PF14) },
173+
{ MP_ROM_QSTR(MP_QSTR_PE07), MP_ROM_PTR(&pin_PE07) },
174+
{ MP_ROM_QSTR(MP_QSTR_PE10), MP_ROM_PTR(&pin_PE10) },
175+
{ MP_ROM_QSTR(MP_QSTR_PE12), MP_ROM_PTR(&pin_PE12) },
176+
{ MP_ROM_QSTR(MP_QSTR_PE15), MP_ROM_PTR(&pin_PE15) },
177+
{ MP_ROM_QSTR(MP_QSTR_PB10), MP_ROM_PTR(&pin_PB10) },
178+
{ MP_ROM_QSTR(MP_QSTR_PB11), MP_ROM_PTR(&pin_PB11) },
179+
{ MP_ROM_QSTR(MP_QSTR_PB14), MP_ROM_PTR(&pin_PB14) },
180+
{ MP_ROM_QSTR(MP_QSTR_PB15), MP_ROM_PTR(&pin_PB15) },
181+
182+
};
183+
MP_DEFINE_CONST_DICT(mcu_pin_globals, mcu_pin_globals_table);

‎ports/stm/peripherals/periph.h

+7
Original file line numberDiff line numberDiff line change
@@ -130,3 +130,10 @@ typedef struct {
130130
#define HAS_BASIC_TIM 0
131131
#include "stm32h7/stm32h743xx/periph.h"
132132
#endif
133+
134+
#ifdef STM32H750xx
135+
#define HAS_DAC 1
136+
#define HAS_TRNG 1
137+
#define HAS_BASIC_TIM 1
138+
#include "stm32h7/stm32h750xx/periph.h"
139+
#endif

‎ports/stm/peripherals/pins.h

+4
Original file line numberDiff line numberDiff line change
@@ -92,3 +92,7 @@ extern const mp_obj_type_t mcu_pin_type;
9292
#ifdef STM32H743xx
9393
#include "stm32h7/stm32h743xx/pins.h"
9494
#endif
95+
96+
#ifdef STM32H750xx
97+
#include "stm32h7/stm32h750xx/pins.h"
98+
#endif

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