lots of updates, easier to utilize main module

Author: XarkLabs

LICENSE

@@ -1,4 +1,4 @@
-UPduino Video Example Makefile Project
+UPduino Video VGA Text Project Example
 
 SPDX short identifier: MIT-0
 

Makefile

@@ -50,8 +50,8 @@ PACKAGE := sg48
 # Verilog source directories
 VPATH := $(SRCDIR)
 
-# Verilog source files for design (with TOP module first and no TBTOP)
-SRC := $(SRCDIR)/$(TOP).sv $(filter-out $(SRCDIR)/$(TBTOP).sv,$(filter-out $(SRCDIR)/$(TOP).sv,$(wildcard $(SRCDIR)/*.sv)))
+# Verilog source files for design (with no TOP or TBTOP module)
+SRC := $(filter-out $(SRCDIR)/$(TBTOP).sv,$(filter-out $(SRCDIR)/$(TOP).sv,$(wildcard $(SRCDIR)/*.sv)))
 
 # Verilog include files for design
 INC := $(wildcard $(SRCDIR)/*.svh)
@@ -73,9 +73,7 @@ endif
 
 # Yosys synthesis options
 # ("ultraplus" device, enable DSP inferrence and explicitly set top module name)
-YOSYS_SYNTH_OPTS := -device u -dsp -top $(TOP)
-# NOTE: Options that can often produce a more "optimal" size/speed for design, but slower:
-#       YOSYS_SYNTH_ARGS := -device u -dsp -abc9 -top $(TOP)
+YOSYS_SYNTH_ARGS := -device u -dsp -abc9 -top $(TOP)
 
 # Invokes yosys-config to find the proper path to the iCE40 simulation library
 TECH_LIB := $(shell $(YOSYS_CONFIG) --datdir/ice40/cells_sim.v)
@@ -126,7 +124,7 @@ info:
 	@echo "    make clean      - clean most files that can be rebuilt"
 
 # defult target is to make FPGA bitstream for design
-all: isim bin
+all: isim vsim bin
 
 # synthesize FPGA bitstream for design
 bin: $(OUTDIR)/$(OUTNAME).bin
@@ -138,22 +136,22 @@ prog: $(OUTDIR)/$(OUTNAME).bin
 	$(ICEPROG) -d i:0x0403:0x6014 $(OUTDIR)/$(OUTNAME).bin
 
 # run Yosys with "noflatten", which will produce a resource count per module
-count: $(SRC) $(INC) $(FONTFILES) $(MAKEFILE_LIST)
+count: $(SRCDIR)/$(TOP).sv $(SRC) $(INC) $(FONTFILES) $(MAKEFILE_LIST)
 	@echo === Couting Design Resources Used ===
 	@mkdir -p $(LOGS)
-	$(YOSYS) -l $(LOGS)/$(OUTNAME)_yosys_count.log -w ".*" -q -p 'verilog_defines $(DEFINES) ; read_verilog -I$(SRCDIR) -sv $(SRC) $(FLOW3) ; synth_ice40 $(YOSYS_SYNTH_ARGS) -noflatten'
+	$(YOSYS) -l $(LOGS)/$(OUTNAME)_yosys_count.log -w ".*" -q -p 'verilog_defines $(DEFINES) ; read_verilog -I$(SRCDIR) -sv $(SRCDIR)/$(TOP).sv $(SRC) $(FLOW3) ; synth_ice40 $(YOSYS_SYNTH_ARGS) -noflatten'
 	@sed -n '/Printing statistics/,/Executing CHECK pass/p' $(LOGS)/$(OUTNAME)_yosys_count.log | sed '$$d'
 	@echo === See $(LOGS)/$(OUTNAME)_yosys_count.log for resource use details ===
 
 # use Icarus Verilog to build and run simulation executable
-isim: $(OUTDIR)/$(TBOUTNAME) $(TBTOP).sv $(SRC) $(MAKEFILE_LIST)
-	@echo === Simulation files built, use \"make irun\" to run ===
+isim: $(OUTDIR)/$(TBOUTNAME) $(SRCDIR)/$(TBTOP).sv $(SRC) $(MAKEFILE_LIST)
+	@echo === Icarus Verilog files built, use \"make irun\" to run ===
 
 # use Icarus Verilog to run simulation executable
 irun: $(OUTDIR)/$(TBOUTNAME) $(MAKEFILE_LIST)
 	@echo === Running simulation ===
 	$(VVP) $(OUTDIR)/$(TBOUTNAME) -fst
-	@echo === Simulation done, use "gtkwave logs/$(TBTOP).fst" to view waveforms ===
+	@echo === Icarus Verilog simulation done, use "gtkwave logs/$(TBTOP).fst" to view waveforms ===
 
 # build native simulation executable
 vsim: obj_dir/V$(VTOP) $(MAKEFILE_LIST)
@@ -173,25 +171,27 @@ $(OUTDIR)/$(TBOUTNAME): $(TBTOP).sv $(SRC) $(MAKEFILE_LIST)
 	$(IVERILOG) $(IVERILOG_ARGS) $(DEFINES) -o $@ $(TBTOP).sv $(SRC)
 
 # use Verilator to build native simulation executable
-obj_dir/V$(VTOP): $(CSRC) $(INC) $(SRC) $(MAKEFILE_LIST)
-	$(VERILATOR) $(VERILATOR_ARGS) --cc --exe --trace  $(DEFINES) -DEXT_CLK $(CFLAGS) $(LDFLAGS) --top-module $(VTOP) $(TECH_LIB) $(SRC) $(CSRC)
+obj_dir/V$(VTOP): $(CSRC) $(INC) $(SRCDIR)/$(TOP).sv $(SRC) $(MAKEFILE_LIST)
+	$(VERILATOR) $(VERILATOR_ARGS) --cc --exe --trace  $(DEFINES) -DEXT_CLK $(CFLAGS) $(LDFLAGS) --top-module $(VTOP) $(TECH_LIB) $(SRCDIR)/$(TOP).sv $(SRC) $(CSRC)
 	cd obj_dir && make -f V$(VTOP).mk
 
 # synthesize SystemVerilog and create json description
-$(OUTDIR)/$(OUTNAME).json: $(SRC) $(INC) $(MAKEFILE_LIST)
+$(OUTDIR)/$(OUTNAME).json: $(SRCDIR)/$(TOP).sv $(SRC) $(INC) $(MAKEFILE_LIST)
 	@echo === Synthesizing design ===
 	@rm -f $@
 	@mkdir -p $(OUTDIR)
 	@mkdir -p $(LOGS)
-	$(VERILATOR) $(VERILATOR_ARGS) --lint-only $(DEFINES) --top-module $(TOP) $(TECH_LIB) $(SRC) 2>&1 | tee $(LOGS)/$(OUTNAME)_verilator.log
-	$(YOSYS) -l $(LOGS)/$(OUTNAME)_yosys.log -w ".*" -q -p 'verilog_defines $(DEFINES) ; read_verilog -I$(SRCDIR) -sv $(SRC) $(FLOW3) ; synth_ice40 $(YOSYS_SYNTH_ARGS) -json $@'
+	$(VERILATOR) $(VERILATOR_ARGS) --lint-only $(DEFINES) --top-module $(TOP) $(TECH_LIB) $(SRCDIR)/$(TOP).sv $(SRC) 2>&1 | tee $(LOGS)/$(OUTNAME)_verilator.log
+	$(YOSYS) -l $(LOGS)/$(OUTNAME)_yosys.log -w ".*" -q -p 'verilog_defines $(DEFINES) ; read_verilog -I$(SRCDIR) -sv $(SRCDIR)/$(TOP).sv $(SRC) $(FLOW3) ; synth_ice40 $(YOSYS_SYNTH_ARGS) -json $@'
 
 # make ASCII bitstream from JSON description and device parameters
-$(OUTDIR)/$(OUTNAME).asc: $(OUTDIR)/$(OUTNAME).json $(PIN_DEF) $(MAKEFILE_LIST)
+$(OUTDIR)/$(OUTNAME).bin: $(OUTDIR)/$(OUTNAME).json $(PIN_DEF) $(MAKEFILE_LIST)
 	@rm -f $@
 	@mkdir -p $(LOGS)
 	@mkdir -p $(OUTDIR)
-	$(NEXTPNR) -l $(LOGS)/$(OUTNAME)_nextpnr.log -q $(NEXTPNR_ARGS) --$(DEVICE) --package $(PACKAGE) --json $< --pcf $(PIN_DEF) --asc $@
+	$(NEXTPNR) -l $(LOGS)/$(OUTNAME)_nextpnr.log -q $(NEXTPNR_ARGS) --$(DEVICE) --package $(PACKAGE) --json $< --pcf $(PIN_DEF) --asc $(OUTDIR)/$(OUTNAME).asc
+	$(ICEPACK) $(OUTDIR)/$(OUTNAME).asc $@
+	@rm $(OUTDIR)/$(OUTNAME).asc
 	@echo === Synthesis stats for $(OUTNAME) on $(DEVICE) === | tee $(LOGS)/$(OUTNAME)_stats.txt
 	@-tabbyadm version | grep "Package" | tee -a $(LOGS)/$(OUTNAME)_stats.txt
 	@$(YOSYS) -V 2>&1 | tee -a $(LOGS)/$(OUTNAME)_stats.txt
@@ -200,11 +200,6 @@ $(OUTDIR)/$(OUTNAME).asc: $(OUTDIR)/$(OUTNAME).json $(PIN_DEF) $(MAKEFILE_LIST)
 	@grep "Max frequency" $(LOGS)/$(OUTNAME)_nextpnr.log | tail -1 | tee -a $(LOGS)/$(OUTNAME)_stats.txt
 	@echo
 
-# make binary bitstream from ASCII bitstream
-$(OUTDIR)/$(OUTNAME).bin: $(OUTDIR)/$(OUTNAME).asc $(MAKEFILE_LIST)
-	@rm -f $@
-	$(ICEPACK) $< $@
-
 # delete all targets that will be re-generated
 clean:
 	rm -f $(OUTDIR)/$(OUTNAME).bin $(OUTDIR)/$(OUTNAME).json $(OUTDIR)/$(OUTNAME).asc $(OUTDIR)/$(TBOUTNAME) $(wildcard obj_dir/*)
@@ -213,4 +208,4 @@ clean:
 .SECONDARY:
 
 # inform make about "phony" convenience targets
-.PHONY: info all bin prog lint isim irun count clean
+.PHONY: all bin prog isim irun vsim vrun count clean

README.md

@@ -7,12 +7,12 @@ example for the UPduino FPGA board using open source tools.
 
 This example is MIT-0 licensed.  This means you are pretty much free to do as
 you wish with it, including putting your name on it, applying a different
-license, modifying it or putting it in your own project.
+license, modifying it and/or putting it in your own project.
 
-Supports 640x480, 848x480 (wide screen 480p) and 800x600, with an 8x8 character
-set and 1x to 8x pixel repeat.  Shown below is 40x20 text (640x480 with H 2x and
-V 3x).  There is an included "hex" font (showing character number in hex) and
-the "retro" Ohio Scientific font with graphic characters (as shown).
+This project supports 640x480, 848x480 (wide screen 480p) and 800x600, with an
+8x8 character set and 1x to 8x pixel repeat.  Shown below is 40x20 text (640x480
+with H 2x and V 3x).  There is an included "hex" font (showing character number
+in hex) and a "retro" Ohio Scientific font with graphic characters (as shown).
 
 ![UPduino generating 640x480 8 color display](pics/upduino_video_breadboard.jpg
 "Picture of VGA monitor showing character set")
@@ -54,4 +54,14 @@ not mislabelled GND, as the silkscreen is incorrect on some boards - check for
                  \-----------------/
 ```
 
+The breadboard pictured is using an
+[inexpensive VGA breakout board from Tindie](https://www.tindie.com/products/matzelectronics/vga-adapter-for-raspberry-pi-pico-esp32-etc/)
+ with 5-bit RGB (hooking up the two high bits of each color to get more
+brightness).  Any breakout designed for 3.3v should be suitable (FPGA PMOD,
+Parallax Propeller etc.).
+
+You can also construct your own VGA breakout with 270 ohm resistors on the red,
+green and blue pins (as shown at
+[www.fpga4fun.com/PongGame.html](http://www.fpga4fun.com/PongGame.html)).
+
 -Xark <https://hackaday.io/Xark>