-
Notifications
You must be signed in to change notification settings - Fork 71
/
rmp_test_stm32f767ig.h
154 lines (142 loc) · 5.82 KB
/
rmp_test_stm32f767ig.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
/******************************************************************************
Filename : rmp_test_stm32f767ig.h
Author : pry
Date : 22/07/2017
Licence : The Unlicense; see LICENSE for details.
Description : The testbench for STM32F767IG.
ARMCC 6.18 -O3
___ __ ___ ___
/ _ \ / |/ // _ \ Simple real-time kernel
/ , _// /|_/ // ___/ Standard benchmark test
/_/|_|/_/ /_//_/
====================================================
Test (number in CPU cycles) : AVG / MAX / MIN
Yield : 176 / 224 / 176
Mailbox : 329 / 396 / 324
Semaphore : 277 / 384 / 276
FIFO : 174 / 232 / 168
Message queue : 510 / 612 / 492
Blocking message queue : 694 / 764 / 692
Memory allocation/free pair : 334 / 368 / 321
ISR Mailbox : 328 / 400 / 308
ISR Semaphore : 259 / 320 / 252
ISR Message queue : 413 / 492 / 400
ISR Blocking message queue : 516 / 596 / 492
GCC 13.2.0 -O3 (SysTick turned on)
___ __ ___ ___
/ _ \ / |/ // _ \ Simple real-time kernel
/ , _// /|_/ // ___/ Standard benchmark test
/_/|_|/_/ /_//_/
====================================================
Test (number in CPU cycles) : AVG / MAX / MIN
Yield : 182 / 264 / 176
Mailbox : 335 / 520 / 324
Semaphore : 288 / 380 / 288
FIFO : 156 / 336 / 144
Message queue : 473 / 620 / 444
Blocking message queue : 643 / 880 / 640
Memory allocation/free pair : 332 / 372 / 315
ISR Mailbox : 313 / 404 / 312
ISR Semaphore : 264 / 372 / 248
ISR Message queue : 375 / 544 / 372
ISR Blocking message queue : 514 / 616 / 484
******************************************************************************/
/* Include *******************************************************************/
#include "rmp.h"
/* End Include ***************************************************************/
/* Define ********************************************************************/
/* Counter read wrapper */
#define RMP_CNT_READ() ((TIM2->CNT)<<1)
/* Memory pool test switch */
#define TEST_MEM_POOL (8192U)
/* Minimal build switch */
/* #define MINIMAL_SIZE */
/* Timestamp data type */
typedef rmp_ptr_t rmp_tim_t;
/* End Define ****************************************************************/
/* Global ********************************************************************/
#ifndef MINIMAL_SIZE
void Int_Handler(void);
rmp_ptr_t Stack_1[256];
rmp_ptr_t Stack_2[256];
TIM_HandleTypeDef TIM2_Handle={0};
TIM_HandleTypeDef TIM4_Handle={0};
/* End Global ****************************************************************/
/* Function:Timer_Init ********************************************************
Description : Initialize the timer for timing measurements. This function needs
to be adapted to your specific hardware.
Input : None.
Output : None.
Return : None.
******************************************************************************/
void Timer_Init(void)
{
/* TIM2 clock = 1/2 CPU clock */
TIM2_Handle.Instance=TIM2;
TIM2_Handle.Init.Prescaler=0;
TIM2_Handle.Init.CounterMode=TIM_COUNTERMODE_UP;
TIM2_Handle.Init.Period=(unsigned int)(-1);
TIM2_Handle.Init.ClockDivision=TIM_CLOCKDIVISION_DIV1;
HAL_TIM_Base_Init(&TIM2_Handle);
__HAL_RCC_TIM2_CLK_ENABLE();
__HAL_TIM_ENABLE(&TIM2_Handle);
}
/* End Function:Timer_Init ***************************************************/
/* Function:Int_Init **********************************************************
Description : Initialize an periodic interrupt source. This function needs
to be adapted to your specific hardware.
Input : None.
Output : None.
Return : None.
******************************************************************************/
void Int_Init(void)
{
/* TIM4 clock = 1/2 CPU clock */
TIM4_Handle.Instance=TIM4;
TIM4_Handle.Init.Prescaler=0;
TIM4_Handle.Init.CounterMode=TIM_COUNTERMODE_DOWN;
TIM4_Handle.Init.Period=21600;
TIM4_Handle.Init.ClockDivision=TIM_CLOCKDIVISION_DIV1;
TIM4_Handle.Init.RepetitionCounter=0;
HAL_TIM_Base_Init(&TIM4_Handle);
__HAL_RCC_TIM4_CLK_ENABLE();
__HAL_TIM_ENABLE(&TIM4_Handle);
/* Clear interrupt pending bit, because we used EGR to update the registers */
__HAL_TIM_CLEAR_IT(&TIM4_Handle, TIM_IT_UPDATE);
HAL_TIM_Base_Start_IT(&TIM4_Handle);
}
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
if(htim->Instance==TIM4)
{
/* Set the interrupt priority */
NVIC_SetPriority(TIM4_IRQn,0xFF);
/* Enable timer 4 interrupt */
NVIC_EnableIRQ(TIM4_IRQn);
/* Enable timer 4 clock */
__HAL_RCC_TIM4_CLK_ENABLE();
}
}
/* The interrupt handler */
void TIM4_IRQHandler(void)
{
TIM4->SR=~TIM_FLAG_UPDATE;
Int_Handler();
}
/* End Function:Int_Init *****************************************************/
/* Function:Int_Disable *******************************************************
Description : Disable the periodic interrupt source. This function needs
to be adapted to your specific hardware.
Input : None.
Output : None.
Return : None.
******************************************************************************/
void Int_Disable(void)
{
/* Disable timer 4 interrupt */
NVIC_DisableIRQ(TIM4_IRQn);
}
#endif
/* End Function:Int_Disable **************************************************/
/* End Of File ***************************************************************/
/* Copyright (C) Evo-Devo Instrum. All rights reserved ***********************/