Add new entry in the mpu region table for increased non-cached ram size

Author: rechrtb

src/Cache.cpp

@@ -238,35 +238,40 @@ void Cache::Init() noexcept
 			ARM_MPU_RBAR(4, IRAM_ADDR + 0x00010000),
 			ARM_MPU_RASR_EX(1u, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_NOCACHE, ARM_MPU_CACHEP_NOCACHE, 1u), 0u, ARM_MPU_REGION_SIZE_32KB)
 		},
+		// Next 1kb RAM, read-write, shared, non-cacheable, execute disabled
+		{
+			ARM_MPU_RBAR(5, IRAM_ADDR + 0x00018000),
+			ARM_MPU_RASR_EX(1u, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_NOCACHE, ARM_MPU_CACHEP_NOCACHE, 1u), 0u, ARM_MPU_REGION_SIZE_1KB)
+		},
 		// RAMFUNC memory. Read-only (the code has already been written to it), execution allowed. The initialised data memory follows, so it must be RW.
 		// 256 bytes is enough at present (check the linker memory map if adding more RAMFUNCs).
 		{
-			ARM_MPU_RBAR(5, IRAM_ADDR + 0x00018000),
+			ARM_MPU_RBAR(6, IRAM_ADDR + 0x00018400),
 			ARM_MPU_RASR_EX(0u, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_NORMAL(CACHE_MODE, CACHE_MODE, 0u), 0u, ARM_MPU_REGION_SIZE_256B)
 		},
 		// Final 128kb RAM, read-write, cacheable, execute disabled
 		{
-			ARM_MPU_RBAR(6, IRAM_ADDR + 0x00040000),
+			ARM_MPU_RBAR(7, IRAM_ADDR + 0x00040000),
 			ARM_MPU_RASR_EX(1u, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_NORMAL(CACHE_MODE, CACHE_MODE, 0u), 0u, ARM_MPU_REGION_SIZE_128KB)
 		},
 		// Peripherals
 		{
-			ARM_MPU_RBAR(7, 0x40000000),
+			ARM_MPU_RBAR(8, 0x40000000),
 			ARM_MPU_RASR_EX(1u, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_DEVICE(1u), 0u, ARM_MPU_REGION_SIZE_16MB)
 		},
 		// USBHS
 		{
-			ARM_MPU_RBAR(8, 0xA0100000),
+			ARM_MPU_RBAR(9, 0xA0100000),
 			ARM_MPU_RASR_EX(1u, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_DEVICE(1u), 0u, ARM_MPU_REGION_SIZE_1MB)
 		},
 		// ROM
 		{
-			ARM_MPU_RBAR(9, IROM_ADDR),
+			ARM_MPU_RBAR(10, IROM_ADDR),
 			ARM_MPU_RASR_EX(0u, ARM_MPU_AP_RO, ARM_MPU_ACCESS_NORMAL(ARM_MPU_CACHEP_WT_NWA, ARM_MPU_CACHEP_WT_NWA, 0u), 0u, ARM_MPU_REGION_SIZE_4MB)
 		},
 		// ARM Private Peripheral Bus
 		{
-			ARM_MPU_RBAR(10, 0xE0000000),
+			ARM_MPU_RBAR(11, 0xE0000000),
 			ARM_MPU_RASR_EX(1u, ARM_MPU_AP_FULL, ARM_MPU_ACCESS_ORDERED, 0u, ARM_MPU_REGION_SIZE_1MB)
 		}
 	};