WIP
On xilinx, yosys does not support yet generating a wide multiplier from DSPs, let's see how to do that, it is a good opportunity to see how DSPs work. Xilinx documentation on the DSP available in xc7 2 is rather hairy, so I aked on twitter and Jan Gray indicated some resources here. In particular, the user guide for Xilinx previous generation of DSPs 1 has some explations, page 33.
A good approach to understand something is trying to reinvent it. So let's imagine you want to invent a building bloc that one can assemble to create nxn multipliers, where n is an arbitrary bitwidth. Let us take a look at how one computes a product:
- Twitter thread (Jan Gray)
- Twitter search (Jan Gray)
- [1] Xilinx Vitex-4 user guide (OLD but has some information on cascading / how to assemble a wide multiplier)
- [2] Xilinx 48E1 DSP user guide
- [2] Xilinx 48E2 DSP user guide
- [3] Compute-Efficient Neural Network Acceleration (slides)
- [4] FloPoCo
- [5] Karatsuba with rectanble mutlipliers for FPGAs
- /usr/local/share/yosys/xilinx/xc7_dsp_map.v