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reg_file-test2.ice
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{
"version": "1.1",
"package": {
"name": "",
"version": "",
"description": "",
"author": "",
"image": ""
},
"design": {
"board": "icezum",
"graph": {
"blocks": [
{
"id": "10679848-0b57-471a-8975-0df0ca5f18ec",
"type": "basic.input",
"data": {
"name": "clk",
"pins": [
{
"index": "0",
"name": "CLK",
"value": "21"
}
],
"virtual": false,
"clock": false
},
"position": {
"x": -688,
"y": -224
}
},
{
"id": "9d5fba98-6fcf-4280-b374-4ededdb8d8da",
"type": "basic.input",
"data": {
"name": "Pulsador",
"pins": [
{
"index": "0",
"name": "SW1",
"value": "10"
}
],
"virtual": false,
"clock": false
},
"position": {
"x": -1096,
"y": -16
}
},
{
"id": "1f74cf56-0106-4ef3-88bd-88ebf424b518",
"type": "basic.output",
"data": {
"name": "LED",
"range": "[7:0]",
"pins": [
{
"index": "7",
"name": "LED7",
"value": "104"
},
{
"index": "6",
"name": "LED6",
"value": "102"
},
{
"index": "5",
"name": "LED5",
"value": "101"
},
{
"index": "4",
"name": "LED4",
"value": "99"
},
{
"index": "3",
"name": "LED3",
"value": "98"
},
{
"index": "2",
"name": "LED2",
"value": "97"
},
{
"index": "1",
"name": "LED1",
"value": "96"
},
{
"index": "0",
"name": "LED0",
"value": "95"
}
],
"virtual": false
},
"position": {
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"y": 88
}
},
{
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"type": "basic.input",
"data": {
"name": "Pulsador",
"pins": [
{
"index": "0",
"name": "SW2",
"value": "11"
}
],
"virtual": false,
"clock": false
},
"position": {
"x": 296,
"y": 600
}
},
{
"id": "edcb9e77-3866-4a75-9552-f99675a0e932",
"type": "basic.code",
"data": {
"code": "//----------------------------------------------------------\n//-- Registers File\n//--\n//-- Dual-port memory: (Read-first)\n//-- * Port A \n//-- - 8 bits R/W\n//-- - 16 bits R/W\n//-- * Port B\n//-- - 8 bits R\n//----------------------------------------------------------\n\nreg [7:0] ram_0[0:15]; // Even\nreg [7:0] ram_1[0:15]; // Odd\n// Port used to read Rr\nreg [7:0] ramB_0[0:15]; // Even\nreg [7:0] ramB_1[0:15]; // Odd\n\nwire [3:0] adr16;\nreg [3:0] adr16_r;\nreg adr_lsb_r;\nwire [3:0] adr16B;\nreg [3:0] adr16B_r;\nreg adr_lsbB_r;\nwire we0, we1;\nwire [7:0] r0i;\nwire [7:0] r1i;\n\n// Address for 16x16 registers\nassign adr16 =rd_adr_i[4:1];\nassign adr16B=rr_adr_i[4:1];\n// Decode which RAM/s will have WE asserted\nassign we0=rd16_we_i || (rd_we_i && !rd_adr_i[0]);\nassign we1=rd16_we_i || (rd_we_i && rd_adr_i[0]);\n// Muxes for 16/8 bits writes\nassign r0i=rd16_we_i ? rd16_i[ 7:0] : rd_i;\nassign r1i=rd16_we_i ? rd16_i[15:8] : rd_i;\n\nalways @(posedge clk_i)\nbegin : do_mem\n if (we0)\n begin\n ram_0[adr16] <= r0i;\n // Mirror\n ramB_0[adr16] <= r0i;\n end\n if (we1)\n begin\n ram_1[adr16] <= r1i;\n // Mirror\n ramB_1[adr16] <= r1i;\n end\n adr16_r <= adr16;\n adr_lsb_r <= rd_adr_i[0];\n // Secondary read port\n adr16B_r <= adr16B;\n adr_lsbB_r <= rr_adr_i[0];\nend // do_mem\n\nassign rd16_o={ram_1[adr16_r],ram_0[adr16_r]};\nassign rd_o=adr_lsb_r ? ram_1[adr16_r] : ram_0[adr16_r];\n// Secondary read port\nassign rr_o=adr_lsbB_r ? ramB_1[adr16B_r] : ramB_0[adr16B_r];\n\n//-- Initial register file contents\n//-- Change them for debugging\n initial begin\n \n //-- Even block //-- Odd BLOCK\n \n ram_0[0] = 8'h80; ram_1[0] = 8'h81;\n ram_0[1] = 8'h82; ram_1[1] = 8'h83;\n ram_0[2] = 8'h84; ram_1[2] = 8'h85;\n ram_0[3] = 8'h86; ram_1[3] = 8'h87;\n \n ram_0[4] = 8'h88; ram_1[4] = 8'h89;\n ram_0[5] = 8'h8A; ram_1[5] = 8'h8B;\n ram_0[6] = 8'h8C; ram_1[6] = 8'h8D;\n ram_0[7] = 8'h8E; ram_1[7] = 8'h8F;\n \n ram_0[8] = 8'h90; ram_1[8] = 8'h91;\n ram_0[9] = 8'h92; ram_1[9] = 8'h93;\n ram_0[10] = 8'h94; ram_1[10] = 8'h95;\n ram_0[11] = 8'h96; ram_1[11] = 8'h97;\n \n ram_0[12] = 8'h98; ram_1[12] = 8'h99;\n ram_0[13] = 8'h9A; ram_1[13] = 8'h9B;\n ram_0[14] = 8'h9C; ram_1[14] = 8'h9D;\n ram_0[15] = 8'h9E; ram_1[15] = 8'h9F;\n \n \n //-- Ram para el puerto B. Copia de lo que hay en el A\n ramB_0[0] = 8'h80; ramB_1[0] = 8'h81;\n ramB_0[1] = 8'h82; ramB_1[1] = 8'h83;\n ramB_0[2] = 8'h84; ramB_1[2] = 8'h85;\n ramB_0[3] = 8'h86; ramB_1[3] = 8'h87;\n \n ramB_0[4] = 8'h88; ramB_1[4] = 8'h89;\n ramB_0[5] = 8'h8A; ramB_1[5] = 8'h8B;\n ramB_0[6] = 8'h8C; ramB_1[6] = 8'h8D;\n ramB_0[7] = 8'h8E; ramB_1[7] = 8'h8F;\n \n ramB_0[8] = 8'h90; ramB_1[8] = 8'h91;\n ramB_0[9] = 8'h92; ramB_1[9] = 8'h93;\n ramB_0[10] = 8'h94; ramB_1[10] = 8'h95;\n ramB_0[11] = 8'h96; ramB_1[11] = 8'h97;\n \n ramB_0[12] = 8'h98; ramB_1[12] = 8'h99;\n ramB_0[13] = 8'h9A; ramB_1[13] = 8'h9B;\n ramB_0[14] = 8'h9C; ramB_1[14] = 8'h9D;\n ramB_0[15] = 8'h9E; ramB_1[15] = 8'h9F;\n \n end\n",
"params": [],
"ports": {
"in": [
{
"name": "clk_i"
},
{
"name": "rd_we_i"
},
{
"name": "rd_adr_i",
"range": "[4:0]",
"size": 5
},
{
"name": "rd_i",
"range": "[7:0]",
"size": 8
},
{
"name": "rd16_we_i"
},
{
"name": "rd16_i",
"range": "[15:0]",
"size": 16
},
{
"name": "rr_adr_i",
"range": "[4:0]",
"size": 5
}
],
"out": [
{
"name": "rd_o",
"range": "[7:0]",
"size": 8
},
{
"name": "rd16_o",
"range": "[15:0]",
"size": 16
},
{
"name": "rr_o",
"range": "[7:0]",
"size": 8
}
]
}
},
"position": {
"x": -440,
"y": -256
},
"size": {
"width": 688,
"height": 944
}
},
{
"id": "7cb9079a-c372-438a-87b4-00fb8e526f9f",
"type": "a6eb6cd34f8e0bc2cb97084941e04dbb8957934a",
"position": {
"x": -784,
"y": -48
},
"size": {
"width": 96,
"height": 64
}
},
{
"id": "0a75a42e-e4ce-4468-8caf-468edc2614f7",
"type": "d3ec3e54382a180944492da9d34569a122cba71c",
"position": {
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"y": -32
},
"size": {
"width": 96,
"height": 64
}
},
{
"id": "e046254c-f464-4da9-b629-eca71299bc51",
"type": "basic.info",
"data": {
"info": "Prueba del banco de registros del AVR\n\nTEST: Lectura de los 32 registros de los puertos A y B simultaneamente\nEl sw1 incrementa el contador del registro actual\nEl sw2 selecciona que puerto se muestra por los leds\n -No pulsado: A\n -Pulsado: B\n \nEl puerto A se direcciona con el contador\nEl puerto B se direcciona con el valor del contador + 2\n \n\nEl contenido de los registro está pre-cargado, para poder comprobar\nla lectura\n",
"readonly": false
},
"position": {
"x": 416,
"y": -288
},
"size": {
"width": 560,
"height": 272
}
},
{
"id": "79c7ce6e-311b-40a9-bb03-b80611dcd256",
"type": "f8ea1906a7edebb7526d63cb69cd933b7155f271",
"position": {
"x": 504,
"y": 184
},
"size": {
"width": 96,
"height": 96
}
},
{
"id": "22674ae2-e98c-4b23-8043-331cf8cc7186",
"type": "d948f3336682e1affec0ca5fbf733a0b1c8b93da",
"position": {
"x": -704,
"y": 592
},
"size": {
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}
}
],
"wires": [
{
"source": {
"block": "10679848-0b57-471a-8975-0df0ca5f18ec",
"port": "out"
},
"target": {
"block": "edcb9e77-3866-4a75-9552-f99675a0e932",
"port": "clk_i"
}
},
{
"source": {
"block": "7cb9079a-c372-438a-87b4-00fb8e526f9f",
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},
"target": {
"block": "edcb9e77-3866-4a75-9552-f99675a0e932",
"port": "rd_adr_i"
},
"vertices": [
{
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"y": 24
}
],
"size": 5
},
{
"source": {
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"port": "ca09a156-6c00-44f0-9f05-b6f883094cc8"
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"target": {
"block": "7cb9079a-c372-438a-87b4-00fb8e526f9f",
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{
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"port": "out"
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"target": {
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"port": "30bde887-830b-4c29-aa25-b5f457ef70e4"
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"target": {
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"port": "in"
},
"size": 8
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{
"source": {
"block": "edcb9e77-3866-4a75-9552-f99675a0e932",
"port": "rd_o"
},
"target": {
"block": "79c7ce6e-311b-40a9-bb03-b80611dcd256",
"port": "2257c1d2-f4ca-4e36-a52d-4c1d36b13486"
},
"size": 8
},
{
"source": {
"block": "edcb9e77-3866-4a75-9552-f99675a0e932",
"port": "rr_o"
},
"target": {
"block": "79c7ce6e-311b-40a9-bb03-b80611dcd256",
"port": "9fa06e30-3244-4096-9758-df8766807d53"
},
"vertices": [
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"y": 288
}
],
"size": 8
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{
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"port": "out"
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"target": {
"block": "79c7ce6e-311b-40a9-bb03-b80611dcd256",
"port": "1e637a79-4a6d-495c-bcac-9664bdbe4b94"
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{
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"port": "c2f82d94-82aa-476f-b40f-f87a1023cc5e"
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"target": {
"block": "edcb9e77-3866-4a75-9552-f99675a0e932",
"port": "rr_adr_i"
},
"size": 5
},
{
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